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DATE: 03-29-2013 HOTFIX VERSION: 0063 o& q0 ?9 A _
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' c% m$ l, b9 ?6 u3 V& m; ~CCRID PRODUCT PRODUCTLEVEL2 TITLE
' I* `( o& l0 q$ H& Q, X===================================================================================================================================, P) t2 I i4 [. E2 Y' j
110139 FIRST_ENCOUNTE GUI Error in Save OA Design form7 s- } X' @2 f; T/ a
625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.
- P3 Q3 g. ]& o642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep I! b" P) Y; l0 [. ^) S3 Z, U
650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".. l* f. ~9 q+ T) `+ s6 [
653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend" O/ l: S: t4 o: |; M, L1 a
687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect
9 O: I/ r/ c6 M% Y/ ]: N0 V" p: l4 r787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics' p8 Z& j& R3 Q% g$ _& x; h
825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
$ K. N! @8 c1 G. i0 |. ^834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming4 ]) `$ b( R6 U$ u6 H B+ u
835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.: e& @) K. k/ j9 j2 H
868981 SCM SETUP SCM responds slow when trying to browse signal integrity
% I: j+ X6 _4 ]% _871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide2 D+ B' F8 J0 H1 F0 m, u: y
873917 CONCEPT_HDL CORE Markers dialog is not refreshed
% K$ a1 D8 q/ D5 ~* B* \- f9 {6 o887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
+ n' t" c# ?: A& C+ c% y0 C2 {888290 APD DIE_GENERATOR Die Generation Improvement
# p7 J8 D# @' d# ]( g; V( s892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator) z+ ]9 k/ X( G
902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice
& }- E7 g2 B+ P+ h! X908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM
4 U6 ?, _9 o b; ]$ k922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols
6 S! m Y' k3 r2 D923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences4 ]0 `+ @" t1 w( s* E3 g3 ~
935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC; p5 s8 q, ^; s. k7 r6 i& Q" J+ A0 X
945393 FSP OTHER group contigous pin support enhancement
- U2 J! ~6 C; I969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database
1 {& ^- e$ [, u8 j1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes$ s* Z, Z( q% o
1005812 F2B BOM bomhdl fails on bigger SCM Projects
7 D' L K5 M+ n) C& U: A1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture
# m# y1 [/ f' u& Y1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names
) h( x! d( Y2 Q7 r3 I; ]$ j' X1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net9 r/ B5 y$ a6 s- d
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
% v: K4 b& |5 A1032387 FSP OTHER Pointer to set Mapping file for project based library.; ] x% b4 \% @ T* B
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 縋LL PLL_3 does not exist in device instance�
[7 y4 `/ D) n1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart7 J' O9 n P/ E1 f
1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding
) k8 r; m& i o$ O( D1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.3 d/ C H7 o) i. x9 E7 O
1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
3 A5 K: n/ f% k* S/ {7 H1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll: ?2 H# d" M$ M/ y& L+ ^% A5 a
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
N- u/ n5 _7 V- M3 w* J- \# g1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects
# N4 o; N+ l- ]3 |/ `; ~4 @+ j1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus2 c4 |& l2 B3 e( q4 Q% U1 l9 }; s
1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts X8 ^6 u, x+ e5 N6 R0 h7 b1 i* K x
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs1 `- Z' J# u! ^/ Y- @3 l
1065636 CONCEPT_HDL OTHER Text not visible in published pdf- K: P& _' G) ?$ J7 u
1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings5 y9 }- ?# H0 k) W1 Q4 S
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary
8 Z0 c- L5 {8 _/ D3 ?& ]1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
4 G# `1 |; [3 u1 A1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
- v; ]' F$ [, j/ ]0 ` Q9 B ]1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down
$ d: K/ q2 M x1 g1 ]5 k1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45. r- [; G- _2 L* r
1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal
( s0 w1 m) T: A3 p: D- K1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
" v6 l) l( `9 g% @, D/ K1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.4 h! R! j( U3 U/ o
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)
: y( g, Q! ]1 i6 B9 e1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die# }& _" s- G# ^+ O; y ~
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
3 S, m/ A9 q& z/ a+ F1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
- c5 G6 |' B+ P5 Q ?. M1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects
: V, }! \( @5 z% B( f3 }1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format
) _! N, S$ p4 u9 E1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net+ ?' f% i/ c, w0 }& G9 z
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
6 t' _0 q- U/ S2 y5 S$ M& L: ?1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible3 I( o5 m L. s5 U" c8 r- ]% x
1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.) s5 \6 c6 C) O7 ~& |; ?
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.& J# p9 z2 |; n! g; ]$ P
1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors
+ o& |; u9 C, |. h2 a5 T1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.
4 u9 z% E5 _$ C' s g% D1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition
$ v& G! m) Q+ U, I; I( a1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor
" E+ l8 e+ S2 v1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
4 R A( f" g0 o( }1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.58 U) A4 X# Q" e8 `8 [. Y- h
1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.
4 P% ~+ V) l2 k$ M1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate
) k# a1 [/ D( X+ X: U1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3, c( B2 W! D% | w( r
1078270 SCM UI Physical net is not unique or not valid
, d$ Q0 P+ _3 ^; [1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted, i1 f3 W" K& K- e
1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle, K! P$ V, n& n O4 a* v
1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs
3 w2 X$ h z: Z1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"
' `4 T: l8 ]9 ^* _1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters/ f9 A' n7 ^6 q) [6 S" Q. F2 }
1080336 CONCEPT_HDL CORE Backannotation error message ehnancement
- F% H# N2 E! h" e6 W5 n1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license4 `/ S- F" h; P( d$ ^7 h. K# o
1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd% r0 ~$ N+ g3 K! O$ K" H6 n
1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error' v: n( { ^! r1 S6 H. o/ c
1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.+ \/ L5 Q" ^8 n3 ?) ?
1081760 FSP CONFIG_SETTINGS Content of 縁PGA Input/Output Onchip termination� columns resets after update csv command% L# |8 H+ F. ^" J! e
1082220 FLOWS OTHER Error SPCOCV-353& @9 u+ |5 U3 `: S3 R5 F: j
1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.: @; J- a1 e) N b/ z# l
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command
! O7 d1 ?3 |0 ?$ ~# I7 G+ j% k1082737 CAPTURE GENERAL The 緼rea select� icon shows wrong icon in Capture canvas.
* j/ X4 O& R- d9 m1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name8 n: G. j w. ]" c+ ^
1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way$ E% D* l+ k3 P; O7 O$ b
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher) U( E9 S, o+ i1 ?, \
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI! x# m& U8 @& ^! j
1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file" F% D6 o. i$ e3 B2 f$ u* t! N/ A6 M
1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.
- O/ W7 y' K1 z3 C8 s1 i1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates
0 ^8 e, L" z+ U8 |6 L! |6 Q7 [1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters
, _# d% m( L! Y1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.$ I. S% B2 U0 |; ]* y$ [. k
1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results* K, X3 c1 v* E* n1 z! A
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.
% |) p2 q* B5 R3 ~7 D1 j8 \1085891 ALLEGRO_EDITOR INTERACTIV about DRC update
. x5 E$ D& q4 d/ J- S% w4 a- j1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO
- ^5 z8 W9 Z% P$ _1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working7 d) ^& d( `8 {* b8 M
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.$ z) D. s9 E5 K8 w5 Q
1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design
/ j3 b+ S y$ q. W% }, Z" s0 V1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated
% e* |8 N* Q8 ^ m" d, n/ H' t1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins2 f( R" R$ a, Y; R) t5 o% K- a. x
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity; t3 O5 N6 |* X% R% }' Q
1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.! G6 T( c/ W- S T( I( o! ~
1087221 CONCEPT_HDL OTHER Part manager could not update any parts.
% X: t& P# a+ r$ Q1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space4 q) x# _5 a' j# t9 J) C8 E6 c0 c5 E* D
1087295 SIP_LAYOUT EXPORT_DATA Enable "Package Overlay File for IC" for concurrent co-design dies too4 Y: F1 Y6 n2 B+ {. f
1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice, d5 R: i) v9 Y5 p! q) [% N/ `$ h
1088231 F2B PACKAGERXL Design fails to package in 16.5
/ U" X+ \7 r0 m) [1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.
1 B+ L U/ N! E# R* W4 K3 l$ {2 h1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor
4 D4 c o7 i7 {$ |8 T% i8 n5 S" o! U+ c% V1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager
9 Y4 ]7 S8 ], I# m/ Q1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?
" R" S' `# ?/ o" i* V. M7 t1089259 SCM IMPORTS Cannot import block into ASA design
$ t" a v0 T/ D1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form7 o' j+ S- C U" n9 h6 @; i$ y4 T
1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project( Z* ^' u2 G# X- k) S8 S7 D
1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory l, }" h8 p& H5 N* H
1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
1 k+ f }( V: a1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
- n' S1 e, s* P) k1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.# v2 |6 f' U9 I* |. q
1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22' G- r2 s, ?# |
1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.; b, a8 G) y! Y4 F
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
8 O0 r/ }6 s) a+ E, @1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled
6 S+ y8 b# ^3 l& G) E1091359 CAPTURE GENERAL Toolbar Customization missing description
8 q; A! k9 W* ~5 L K' L- t1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive! C% ~1 d8 d \! Q
1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time
' d6 H& }! ~/ ]5 i3 d1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.56 K X* w2 I/ b2 l9 n6 U. N
1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design
; \- x' _) F( N3 I% {, Z1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled
3 ^7 o7 A% J5 x* \3 o0 B8 f1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters$ r& `5 l4 k- B( c+ \
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error
t2 D" \! C& k* u& {1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder
2 X% {6 V# N6 x- P3 I1 S- {1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor0 X t! d$ L3 A0 ^. S' a% }1 h& k
1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.: }" S% \, z) E+ Y8 [
1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time
: V A1 U) T" E) y! z: u1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.
& t% ]7 A1 ?! u0 V1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
P; `& z4 P' X+ R7 C% \1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic
2 X8 ^& ~: f) e, s1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5% { ~7 y% j& y" F! p h: D
1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet: [, G+ N! i7 P# I
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die$ A( q4 F$ I! y7 \9 e) I
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block- a: L! D$ n5 j" d
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
8 L4 n6 q8 N l1095861 F2B BOM Using Upper-case Input produces incorrect BOM results% a. a" q# }* l4 t6 G6 z
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import6 v1 U8 D9 r% x& _; a
1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically: A, \; T" c9 t. x5 W; ]' n6 H& V
1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias8 r V: c. ~9 k0 X# A& k" C
1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate0 s7 M! J5 z6 o8 p# J0 A- X3 m
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors* w6 ?% A# E" G% a- ^# y
1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL
8 D0 P5 Y. d- \! C3 R1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.& u, S( `( W* S8 `( } b
1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side
: i$ j1 W5 ?+ e" y1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command
* h' O8 q1 @* j+ Y z$ ~8 V$ ^1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
. d0 h4 Z2 Y6 v6 D, L- X1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives k/ D) \) Y6 ~1 [' O% X/ ^% h
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork: X: R* Q- X5 j- D6 @8 L/ S( M
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts% _7 S% @- W: X! r8 V7 K& T
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
j- _+ O+ q, s5 ^1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.7 m J# j1 X" m M$ V/ ^* T# x" X
1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties/ d% C7 J2 u. E) A$ k
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6
) q; h. l# k0 e/ k1 [1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad3 x; W! d; ]" E3 Y+ s) H4 p. {
1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
8 z" C$ Q8 g+ Q" l1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad \ a% H0 W4 u' Y6 o; I
1103703 F2B DESIGNSYNC Toolcrash with Design Differences
' q/ h3 r" u0 m& h$ d3 g, M1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view) b) G, n4 N L% Y4 ^* A
1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.60 |+ w- `- Y0 Z7 M: `
1104121 PSPICE AA_OPT 縋arameter Selection� window not showing all the components : on WinXP' U) V/ ~) b* [7 { Z
1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly
; K6 c2 ^- S" J* s1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM' R0 @7 }" ?- y- S; v/ W
1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.
( G8 F' e: y& H% G# u/ m1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.) \* J; t; e- _4 \" q$ o% S
1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form
4 g7 o& @2 K$ D9 r1 u# V, m1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part; M6 g1 a6 c" F7 s, |* L
1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked
# q* N( _+ s9 i: C1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
: ~+ R& \2 ^% I' o M5 t1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6& V) e! b& E3 c6 C$ J3 d2 Z, F2 a; s
1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only' [2 a, {: d7 q$ E: a( p' Q# N, T' P
1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid" N) @" P' S' l c/ L( ] P% D
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.8 f" e$ u1 S6 x- x0 O: y2 T
1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param7 _; ^. g% f+ j$ s {( p: w4 _
1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish# K9 K8 h8 q& F6 r7 G& r
1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).
* W1 @2 h7 {2 O1 U0 t6 ]1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke& y5 i. M1 m3 G; b" t+ Y0 s2 w
1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
& i, d& N% ?) m3 u4 ~/ R1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode0 ~+ M6 Q7 q. g/ b# j
1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs
& a! L" ^4 Z, o7 Q I5 t) o1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6+ X1 J0 ^8 H8 W
1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.
/ M* t0 E/ v* M3 n3 c1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
6 L! h7 M/ n' l6 j. K9 }1 m1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
( N) D2 P4 t; Y# k4 h! R- j1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset* X( x9 c9 X9 ?. L! u
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters
4 w& v$ Z, a0 R; s* \) f3 O$ K* I1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend# |& q7 I- v3 I) X* y1 X3 s: B9 k9 Z
1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP+ Y) p- D, D1 Q/ i5 V
1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint ~. v, c+ L) g8 Z$ E4 J9 W$ \# O
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan# C6 S" c& s- @( w
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.' w+ U, _$ W. @4 F# U
1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file" u. y% `, c! t) c v
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6( X( X$ z. }- U# i$ \0 C$ V
( V- d9 w% b# J- w
DATE: 03-7-2013 HOTFIX VERSION: 005
3 v+ C: x3 U$ f% H. x) `, H===================================================================================================================================9 b% [' j, b8 [# \$ _
CCRID PRODUCT PRODUCTLEVEL2 TITLE, a1 @# k% g" T) Y2 R& K
===================================================================================================================================* v; t; X& j, @6 K. B6 P6 ~% U
1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 11027 o; g X- t5 |9 P" Q8 W" d- k
1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed
. ]- A; R( V0 E# g5 c- v' n* _1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently3 ]$ ?0 G1 k% A% C' v
1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind* f: p$ x+ v8 W3 S* k2 }
1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view
! k; [' _' H4 s1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed
( u% W! s. w, R. }1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM5 g c$ [" z* W# g/ i7 B
1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.68 E# y: p* N4 V7 L0 e( y
1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement.
1 X! G, `) x: t' f1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design
/ { B, w* Q: k0 M$ z1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional: Q( o4 F: o9 T0 r1 y
6 t) M8 T) r4 v% r
DATE: 02-22-2013 HOTFIX VERSION: 004
. u/ m' Q. f; g$ G===================================================================================================================================4 z, i9 J1 G3 g# u. ?9 ~$ y
CCRID PRODUCT PRODUCTLEVEL2 TITLE& \, u+ }' k( S* ~
===================================================================================================================================5 p* t7 C) x: z$ N. F/ l
1081026 ALLEGRO_EDITOR GRAPHICS 3D Viewer do not show the height for the embedded component correctly9 ~0 f7 k% j* Z4 f9 H9 M0 c: U
1095225 ALLEGRO_EDITOR EDIT_ETCH The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing8 k8 y0 u i+ {+ \, y/ R
1096356 ALLEGRO_EDITOR DATABASE Cannot Analyze a Matched Group in CM
; }+ T) V2 m6 ?1097481 ALLEGRO_EDITOR INTERACTIV Allow replace padstack command in design partition
3 Z7 M9 S7 P5 x+ `; h3 |$ p1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend
9 R' R8 S- n* Q$ [. W0 _1099958 ALLEGRO_EDITOR PAD_EDITOR Library Drill Report producing an empty report
. i4 L5 a5 a% W/ s1100401 ALLEGRO_EDITOR OTHER Invalid switch message for "m" for a2dxf command
9 T* q% x3 @9 q1 D1101026 ALLEGRO_EDITOR OTHER utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit.6 n7 q4 Q; h2 @" j/ x! X. q, h6 T
1101064 SIP_LAYOUT SHAPE 'Shape force update creates a rat% d [" G Y2 O( P+ n) {; k4 S X6 l
1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated.
5 @# z8 e) Z3 L- G! W7 `; x" u/ N7 b
7 }5 `/ ~" I/ ]0 ?. A8 JDATE: 02-8-2013 HOTFIX VERSION: 003
8 G( S% z# {3 V1 k" w===================================================================================================================================
1 u/ c b8 o s9 Y2 _# f8 CCCRID PRODUCT PRODUCTLEVEL2 TITLE4 @# `; C3 |% B( W$ N$ {) r7 B
===================================================================================================================================' h: V+ D! q o: e" W! C! E
1077728 APD EXTRACT Extracta.exe generate the incorrect result! Z6 c) C9 j3 Y3 `) @& W
1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF' ]$ f& B) `& o# u' G, P( q
1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer1 E6 o; s. e) n, q
1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing., \* m& H. R0 y% ~' U' r6 ?3 u% S
1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on ?: U1 {- U0 j2 I$ s% e
1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent
3 X" p. a2 N' M6 m$ [1 L6 I1094788 SIP_LAYOUT WIREBOND Wirebond edit move command& P9 T0 w; ?% |8 z2 Z: K
1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor" }1 @1 c' }$ S8 P% t
1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn縯 show up after 縎uppress unconnected pads� option.: W) j/ G$ f6 @" V/ k
1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff: b) b7 m) T8 T
1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible4 u5 D& {; a! V" n7 L$ O
1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35
+ S; c: v5 K2 J2 b* b( G4 F2 d1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.
3 ?) K0 F7 `. X8 z* D7 \7 p1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.
- k b t3 [/ j9 X- I+ ^1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license., y, s( Y0 v3 X7 k7 W6 l
! d! t7 ]4 C1 D7 W0 h; ], D4 UDATE: 1-25-2013 HOTFIX VERSION: 002
T' j- t6 ?# [0 U0 ]===================================================================================================================================
" \. h1 g9 {2 |" DCCRID PRODUCT PRODUCTLEVEL2 TITLE- G5 D; _8 r% X2 X5 L' b
===================================================================================================================================
* g+ d5 ~6 v4 g' Y2 i0 |$ X491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute
7 A* A- T/ O5 h1 T( v9 Y$ X5 {863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc") J/ H0 Z1 p/ p) H, {
1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes5 }0 W" w. ]0 n. q) C% |, h
1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable
( \+ z; L. m0 j. h8 m3 U v1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33
" @ e# p$ ~/ B1 F1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence& G' r! M) R& D7 U1 t3 R
1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator
" @0 U) Q+ i6 i! b5 S, Y: V+ z& \- ?1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command
; Z7 b. @. B, k3 i7 [& o2 X+ m$ J# J1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.6- ?" L0 G O7 u' d6 o
1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note.3 q7 g% t; u k2 F) F
1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.- g/ a7 ^" l' x$ g" K- N$ M
1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL./ v- G+ Q% t/ X. z, k/ Q
1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0
* h5 o! e2 d& z# N9 c3 A1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white
0 z# M) N s/ n1 o( [4 C1 p& e1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure2 F. F" U9 X, `- r8 b6 g
1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer O% L3 f/ p: h6 k1 Y- \
1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile.
; E9 J( V0 Y: K+ F! G' }1 w/ d1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.* a. \6 b" W6 \# j
1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name.
/ Q- W! l1 o2 F; b5 F, K1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.6( Q1 l4 G3 ?# M. @. [. ?3 C3 e
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout7 B: Z6 \% \: p: F* d
1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file# o- w' A7 Y* ^1 g
1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing.
$ y" u5 e; a7 _0 M) f1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.
/ u2 s$ K1 x& w J/ E# \" }1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties
7 ^9 `& t/ r# ]7 N1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error! u, I; C- t8 t& `" ?# |
1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric" K* _/ u9 s# T, ]+ I
1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.6 S& t5 o9 x- x% f# h5 U
1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue
" c! d$ J* ~% _3 Q! n6 N: k* l1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command- w( \1 g9 S9 N0 U# q' O6 O+ U
1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled* u' }. O7 c8 O2 W
1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error' P6 H! n0 N# U
1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled./ m6 x, `! C7 r ?" _6 n
1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function
( j+ e- H% Z. d( Y- H6 h1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command.* E0 Z9 O. \5 U6 i& Q& x
1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames?6 Z9 E& g/ e6 ^" k8 Q* w
1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group& Z" D |- i+ l1 Y4 v8 o
1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle
6 n0 d( C* L& }( y% I7 [1090689 ADW LRM LRM: Unable to select any Row regardless of Status
- T) T) C0 _& i1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle
/ A. z6 u; [' ^1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas.
: E. J1 K& {2 p3 w. }& S% p2 }1091218 ADW LRM LRM is not worked for the block design of included project
, a$ ~4 ?$ i$ r4 Q1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads
& ?, T+ X' w0 a; F# `6 r0 a. l! m1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width
) t2 B1 g$ ~" T1092916 CAPTURE OTHER Capture crash/ I$ A" |" j6 u
1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database
- m; r( ^( e; q* R* s7 q
. z0 n/ r5 K4 q1 F9 U3 YDATE: 12-18-2012 HOTFIX VERSION: 001 F$ c2 P* _$ O. Y4 l% ~: ]
===================================================================================================================================
" F' b/ h( x" c2 ^7 DCCRID PRODUCT PRODUCTLEVEL2 TITLE
3 @: ^8 {+ L! G===================================================================================================================================
! v% V. b6 R* E) w, K& [501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap Y9 ~' }8 J5 E3 n. i. N
745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched* q, l. `6 y! `! v
825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted5 L s9 L a9 ~; ]6 ^* C9 K
871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash
6 E4 }) z: j* ]5 f% ?+ ~/ S4 y891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
" ?" F! n3 X0 c3 e- J898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore6 L( N" @' i0 F% {: Z
923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties
8 W8 F. M( e4 `! @- s% c, z4 G938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
* X# X2 [, H- O% i947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.
' x* G8 B2 n: Q6 W) H968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing: I( _6 K7 H" n+ a
976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor# O+ l# S" {: P0 O6 Y. U
981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.% H9 t5 t7 ?- v4 R# o
982273 SCM OTHER Package radio button is grayed out
1 m6 T$ w _4 l; N9 ~988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
# b1 C* ^5 o& H0 N' ?989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode4 x, Y8 Z! @: o4 Q( }6 \
993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
% m3 O5 l2 m1 v( b/ Z6 u+ a$ K9 x996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections6 C0 `+ H% O. @5 U/ m
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
1 t# j h: B! y1 f' b X! g' ^+ E* Z1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model: V8 a# Y: r- j4 x
1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs
5 A9 T* e. H1 _4 q! o+ \+ t h# C1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg
* N, H" L) a# h3 B& h1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.6 p6 t$ x/ F' w/ k# e, o
1016859 SCM REPORTS dsreportgen exits with %errorlevel%
) Y2 |2 `- N/ N$ P1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin
H( a; P- ?8 c0 t1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs
' y: G/ `: e& o1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts+ B1 @* O/ I6 P8 S7 a
1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
2 g2 O7 N# n' l/ g1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.
/ o* Z# z% S4 `; @& T# V' C1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
( s4 R7 W/ c; a2 x1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out
e5 l( q X6 g( m* N1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist; O! q( M& p# U; L
1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed
. K& J- F$ U$ j- F1035624 CONCEPT_HDL CORE Options pre-selected when launching base product2 X5 r/ Z; h, r& q3 s) R9 e
1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly
3 z4 b( U' ?" ]3 d1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.
/ M/ m+ ~8 }- d1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
" i# X0 O4 a; R0 l' [1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol7 Z$ X1 c0 a/ ~; R" C
1038285 SCM UI Restore the option to launch DE-HDL after schgen.* d l& I5 _: i2 R4 a
1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."' `# R6 {0 f! s+ u. M1 `
1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro
5 D3 W& G) }. n7 s% J# ?4 N1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected
% }; w/ U9 |7 @$ j6 W {" w1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing8 ~8 r; }# P+ H9 ~- O7 {0 D
1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.* U5 H/ }: C1 f/ O, ^ @
1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.
1 O. u# y7 I) B3 W1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu5 u3 X O* I# ~5 b( V5 k& a( U- |
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.. a* G1 o+ e# }' Z0 s
1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow2 u: ~2 ~, q* U) @/ D
1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory9 k% D/ o9 t& r$ N, \+ Q
1043903 GRE GLOBAL This design crashes during planning phases in GRE.
$ s, s# ?: f% S. v( F3 q! [+ s6 K1044029 PSPICE ENCRYPTION Encrypted lib not working for attached/ U, k: b" C" F( A5 U) s
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
0 k6 X _$ c* G* ^1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.# W9 a# z) Q* u' r* T
1044577 GRE CORE Plan > Topological either crashes or hangs GRE$ S* Y6 {# n, J- } p8 @8 R
1044687 TDA CORE tda does not get launched if java is not installed
, e7 U7 x" W! s1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die; h* v1 F+ `) y# g+ I- P
1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.6 K) \6 [6 v0 D% d( y3 C! c, V
1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?! \: m% v# t* `- J) d
1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.
( t2 G7 |+ M9 k0 J7 }* j3 w9 g2 t1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.0 }5 x2 f7 m+ i# a
1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow
$ g2 g) F- \8 z/ y$ i1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.
0 W& g% W3 ]4 f. g5 Q& k1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill4 T0 Y/ Q6 g8 }
1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.3 b5 p$ u! e# Y$ ~$ P3 _
1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5
q4 B) j9 F6 N8 j1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5
; [0 t9 o& b5 v; m2 P8 k" J& p1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value
2 [& F: X" g6 [/ L1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version
: l# ]& w8 W9 m+ Y- f1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯.2 X" R% k: I2 u
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
0 S6 L9 w# `- T" _3 N! _" n1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.
' ?1 U P3 x3 T9 T4 q9 q1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes
2 G" T0 k/ r. n& `6 i# q1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.7 X# T- \3 H2 r! ?% }. P
1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3" j" Z+ I4 c. J2 v T' W, V
1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file/ v; [6 q. H% O9 u3 ?
1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors
6 h3 D) ]& I$ C) {5 {, _1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.5 @# b' {- Y/ s$ d2 n# I2 O% O
1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.
6 q6 b) x' a+ Y* `& H$ l1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design0 L" P. R: r' A% [3 y
1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs1 c. B7 u: R- ?/ R& v! {$ m
1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label
$ Z5 p# `2 z( L- ~3 R6 c2 I1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.
& s9 t- C8 ?* S0 Q1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy A2 P4 N w+ D& y1 h
1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down
S0 _4 ]* L) c) m" l1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection
9 ~! F3 J. g3 \1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.
! W1 a, [: K( j1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views
4 C' D1 s+ Y7 v. R# M1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline
; Y9 ^5 L2 E9 [% d0 F" O* t* T1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.
; d9 \" _, }+ s5 [1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created.8 H: Y$ I0 z" H6 E- u
1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move7 O( T, r* D( z( V
1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value
: i5 b3 U- B0 j% C( B8 a4 ^1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer% s2 t1 R' |" P1 e7 K/ g5 R8 D
1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report( o" m+ F b! `$ w! Y
1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.' b P# a% x' j8 @ E1 J: D
1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete
5 N3 J! C. E: m( g( m7 b1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
9 _# m5 q7 F5 G2 \1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets
4 a& W. a8 i4 }- h5 H0 G1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?
0 y' w4 f5 [5 p& x% o1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.
* q; q n0 U- d9 q1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.# Y- K7 T& Z* i8 N0 @
1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 005 M1 } k+ t- \: P$ K }0 U0 G& l
1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation; T( |* l5 b; i
1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.
9 G1 W" T2 c$ j3 Z1 x! Q8 L1063284 PCB_LIBRARIAN OTHER PDV Save As is broken6 r' Y$ c0 ^) t K
1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs; v, [0 P0 {, c
1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.3 {) O$ _) s1 Z/ X
1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.
% `8 W$ R" X) m2 ]0 ^1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design
( B& d" x. ^* N6 i1 O1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV. Z- ?! q3 C: C) j* ~/ ?' r$ C4 Y
1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.
! K! X3 q) d% D1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X9 M$ \* e3 ^" h0 O9 }5 `
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application7 g' d5 w) k7 v" ~; n( \; f6 p6 ~6 \
1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report
3 i8 R' n- H) w0 r) L6 e1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC% c1 k+ V; T' _ q& \
1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic4 Q/ {* R1 A6 Z2 h3 s* [
1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.: O4 }& i; ~& w, U# m7 }- ?9 }
1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file
% `5 h7 ?* h4 p0 k: ^* @1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command5 L4 V+ x% w' K3 i1 d: Z
1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended' o4 _5 f0 `: A1 A D# S) Y
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067
& u S/ g, B! V# m1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design, L# s) T- | b6 V! [$ c" Y4 g
1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify, C- f: ?( v5 G& _9 }
1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids
- b# q( ]/ `6 q( A& o" b9 `1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes' A2 h3 v8 ~' K3 i3 l" r' `
1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
" a: e5 D: M7 d$ T o# m1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal7 a* |0 L1 b. I+ r3 e1 q- u$ b
1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.' V V) F5 B7 e5 ]
1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6
, [. e9 U8 Z+ _; [0 p4 p x1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5: y2 H u j6 C+ C, v
1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.+ |! l: G( G& b4 V: {
1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.& n! e% ~# U+ Y+ R" G
1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor3 j7 U- s* B) J$ G' M. G
1073464 SCM SCHGEN Schgen never completes.
- f$ T( ], O! f3 y1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory% z: x; @ I, P
1073745 CONCEPT_HDL CORE Import design fails+ i- Y3 P# m. v) o8 q0 K
1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'
/ i) J# W$ E, A+ R/ O1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE( N5 v9 @( v7 F/ h" [( s" W- W
1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist. `5 Z+ Q& I4 W8 J
1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter
; O* d: T& \( {% V8 [ x3 q* G1 [1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
/ z4 [* G4 g; N: A( H1 i1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.
" T: U2 r; \ H, S2 [/ ]1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI
y2 h- R: X# F1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block C' a9 ]( S* a1 h
1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer# s. e9 q' i' W3 J
1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces
6 T9 {5 n* @" T. ]# i5 g1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2
% e& \, n4 b @0 I: D8 l1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix
( U7 h- C7 n$ o* e! g. h% J1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
) B& P8 |1 F' ^- U! p, d9 t1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top
5 ^+ Y5 e7 \% p8 ^ }/ Q1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.
; \! a6 c/ x6 v! U" p1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value+ q) ^ Z! |, ^! n/ Z
1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.6
, ^7 r% C5 z& S+ w; d1 I' O1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey% C0 v4 ^" p5 x' n, n$ P6 r
1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database
; @1 j; u7 c# F' v3 Y T5 R. T$ G1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset" g9 R. T0 ]2 F# d) b; u0 _+ X& x
1077169 APD SHAPE Shape > Check is producing bogus results.
0 }/ K5 A* M/ a( }8 H( {1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board., H4 r \2 I3 K' f7 a0 J
1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim
& E5 C/ Q1 L! x, I6 H6 I1078380 SCM OTHER Custom template works in Windows but not Linux
6 T* c: Y6 S. E* _1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.4 _' Y# ]2 e) }3 S
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide6 D" ~6 S7 e& K! Y# z- v3 w$ y
1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
4 H6 X+ p4 p* x! u1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"
O( H: ?* R, h3 P7 g1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text6 E$ m% a; G% ?6 M2 c" F
1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control
' G" V* m) a" T$ O9 a9 F7 u1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical./ F6 W7 C7 g5 V* O
1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.
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