标题: PCIe 4.0 传输速度上冲 16GT/s，你准备好了么？ [打印本页] 作者: doya 时间: 2011-12-2 13:58 标题: PCIe 4.0 传输速度上冲 16GT/s，你准备好了么？ PCI-SIG组织今天宣布，今后的PCI Express（PCIe）的行业标准输入/输出（I/O）技术将采用新一代的PCIE架构—— PCIe 4.0标准，该架构的带宽将是PCIe 3.0架构的两倍，达到16GT/s。PCI-SIG在经过了一系列的技术和市场分析之后认为，PCIe 4.0标准将继续使用铜线工艺，并且带宽双倍于PCI-E 3.0、同时两者在功耗上保持基本不变。各项技术指标也证实了16GT/s的高速带宽互连完全可以使用主流硅处理工艺制造，所需成本也不是很高，并兼容上代架构。( b/ `( ~9 b' |1 B( R) C+ j3 x
此外，PCI-SIG还将会对主动和空闲功耗优化技术进一步深化研究，而这也是当前业界面临的关键问题之一。 4 t$ ~8 B% s: t q3 u w* R9 U& k* g4 N( _7 Z5 n
作为一个开放的总线标准，无论是现在还是未来，下一代PCIE架构将在提供高速带宽的同时，将继续保持它高性能低成本的地位，并且保持向下兼容。PCIe 4.0将会解决诸多应用难题来推动低成本高带宽的实现。凭借自身优势，PCI-E 4.0标准将进入各种领域，包括服务器、工作站、台式机、笔记本、平板机、嵌入式系统、外设、高性能计算系统等更多领域。PCI-E技术人员在对下一代PCIe架构仔细分析后认为，16 GT/S是一个完全可行的技术解决方案，并且将继续保持低成本。 . }' w7 L: [& X y. F+ A- P3 g8 S* X# O0 _" T# k
据悉，PCI-E 4.0架构标准（包括形态规范升级）预计将于2014-2015年的某个时候最终完成，我们拭目以待。作者: stupid 时间: 2012-7-30 13:20
Gen four is coming! Hide.* ^" ?( w* O7 K% S! R! s
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Al Yanes, President of the PCI-SIG (Peripheral Component Interconnect &endash; Special Interest Group), held a party in Santa Clara last week to celebrate “Twenty years of PCI technology and twenty years of innovation.”' H$ h( v3 z/ v4 X# C0 S
5 v! e j9 k; w; i7 u" H1 FRamin Neshati, the PCI-Express Serial Communciations Working Group Chair, said “All future client-based storage attachments will use PCI-Express.”2 k) j" K( O8 n9 D; s4 L
8 S; I) u$ F/ Y' G7 D& tYanes and Neshati introduced plans for PCIe 4.0. Here's a summary of the generations: 0 a- V2 n8 B, g; ^1 }. }% t- ?! b H/ x# W/ w+ W9 \
• PCIe 1.0: 2.5 GT/s = 2.0 Gb/s with 20% overhead from 8b/10b encoding. & [7 j0 G, H9 K6 @! [• PCIe 2.0: 5 GT/s = 4.0 Gb/s with 20% overhead from 8b/10b encoding. 0 ?" Y: }5 x9 b6 M
• PCIe 3.0: 8 GT/s = 7.88 Gb/s with 1.5% overhead from 128b/130b encoding.1 r9 M& |: l3 M& t9 F# g2 @" r
' `7 q0 L/ \% I1 [( gAnd new PCIe 4.0: 16 GT/s = 15.76 Gb/s with1.5% overhead from 128b/130b encoding.! V* G" i6 t5 G8 |1 w
9 m+ c" v5 Y) I: \7 M7 N* BEvery generation supports multiple signaling widths, scaling the available data rate by introducing more lanes: ×1, ×4, ×8, ×16. 1 \+ V( [& v& o- e1 r: R: {) f y u9 f% S& R
Backward compatible to PCIe 1.0, PCIe 4.0 will follow the same essential rules as previous generations, supporting up to 32 serial lanes in one connector. The upgrade from the first generation, which has 2.0 Gb/s at 2.5 GT/s, will support ever thinner devices. One lane of PCIe 4.0 will support the data rate of the ×8 version of PCIe 1.0. And fully loaded at ×16, PCIe 4.0 will be able to haul a tidy 256 GT/s. # [% J! w. F8 Y7 t& S0 U; y / g! Y! \) c: V$ h; qThe PCIe 4.0 specification will support cable lengths of 1-2 m and 8-10 in on standard FR-4 PCB (flame retardant type 4 printed circuit board (i.e., the same stuff you've been using all your life)). Users are welcome to extend the reach at their own risk (and reward) and they are considering including a standard for repeater technology to ease extensions." ]- I* w7 X; X' y
; u+ N; x. r* O' Q# J) X$ ?3 a9 [Neshati said that the bandwidth improvement from 3.0 to 4.0 will be attained through improved silicon and channel improvements like routing geometry. They will "reoup lost margin in the connector." The new connector will be mechanically identical to PCIe 3.0, but electrically improved and backward compatible to PCIe 1.0.* \& s! M' p' ^+ c* ^
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Neshati added that he expects "PCIe 4.0 to be more of an implementation challenge than a specification challenge" by virtue of the unique tack that the PCIe standards committee took in developing PCIe 3.0. Rather than prescribe interoperability standards based on acceptable worst cases, they embraced statistical analysis so that the standard could address only those edge cases with a reasonable likelihood of causing BER (bit error ratios) to exceed the prescribed minimum.8 q6 @2 J u& M
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Referencing the rule of thumb that roughly five years passes from initiating a specification to delivery, Yanes said, "Expect the PCIe 4.0 specification to be released in late 2014 and to impact designs in 2017."