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library IEEE;6 U0 T m% Y9 e
use IEEE.STD_LOGIC_1164.ALL;2 S1 z9 T1 C6 f# R4 N
use IEEE.STD_LOGIC_ARITH.ALL;; f2 g2 k" q1 W
use IEEE.STD_LOGIC_UNSIGNED.ALL;6 c# L" g' ]9 k: k
entity spi is # k, k6 u9 O( R( }: P8 E
port
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reset : in std_logic; --global reset signal
3 }# S% W/ ^) E6 e" [0 ~2 J" b1 x sysclk : in std_logic; -- systerm clock
+ f* T6 @3 Y# T: V" p data_in : in std_logic_vector(13 downto 0);. S* {% J/ I" p, X; @
spi_o : out std_logic;
8 M( E, }: Y3 d' c+ N5 ] sck_out : out std_logic;/ z1 S$ ^. ~# g+ e
ss_n : out std_logic_vector(1 downto 0)
[' M l% b$ ^: C' Z% `5 W; F );4 o5 g# |) S. C: y
end spi;) t- `+ I8 D* \4 R5 L5 D$ I5 X: c
architecture b of spi is' Y& _3 S, x" F. x& Q; ?' N
type state_type is (idle,shift,stop); -- data type define
! j# v( G, ~4 P2 I( A' K( p% P$ c signal state : state_type;
+ f) @, n$ ~! n" L# S" H9 E: M3 B signal out_reg : std_logic_vector(13 downto 0):=(others=>'0');
. o0 w2 ]% d& o) V4 o2 w signal clkdiv_cnt : std_logic_vector(3 downto 0) :=(others=>'0');3 `6 M4 f o* w: H6 R4 a
signal bit_cnt : std_logic_vector(3 downto 0) :=(others=>'0');& d" D( s2 g% H- E. ]' L
signal sck_o : std_logic;* ~' Z3 b& b s
signal full : std_logic;( ^2 Y- a6 w! z8 n% C1 }- d
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begin6 I7 b% W; {5 w
sck_out <= sck_o;
6 r* Q! X1 F) V! h# t process(sysclk)
/ A$ F W* ]7 a. y" s* Y% B2 _3 P begin
# ^- X! |2 _' @% U: b8 H if (sysclk'event and sysclk = '1') then --reset
8 k/ e' u- b- D. p! R( n2 E% `8 ~/ i5 [ if (reset = '1') then
) E; \ j/ T+ C" C, D3 R! z ss_n <= (others=>'1'); --AD5553 idle CS =1
0 ]& D! _. g" _& K out_reg <= (others=>'0');9 f/ _& C) J$ ^8 V
clkdiv_cnt <= (others=>'0');
5 h& c3 `( V0 K0 T% x3 d bit_cnt <= (others=>'0');% u/ t6 t8 T7 `6 \5 q x
spi_o <= '1';
/ F+ t9 k7 l- ^+ H7 ^( ^ sck_o <= '0'; -- AD5553 SCK idle is 0
% z9 d: l' c% f" O6 K% o4 u# l state <= idle;
( N5 K, \. N: |# M* }. ~% z full <= '0';
" o* F2 l) s. e/ i else ) T$ ?8 p9 L1 E1 u# B) ~! L
if(full = '0') then. N0 N/ U3 W% j8 W: A5 U) Y
out_reg <= data_in ;1 Y2 @1 p* p$ a% P
full <= '1'; `, E+ D7 w' U! u7 N/ k# O# F
end if;
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case state is 8 T E$ |+ k9 B" b$ ^
when idle =>* l. A; V7 U x* l1 N0 c& c/ z
9 x/ O6 |& R& w state <= shift;
* C" z/ q! O9 Y1 {+ Q spi_o <= out_reg(13);
0 Y, x v; l. x' ~3 l3 j$ I out_reg <= out_reg(12 downto 0) & '0';9 ]4 z4 m/ y; O% R3 L; @) r6 \
sck_o <= '0';
' I' e$ \2 G$ E' |( u; ^# v; e4 V; ? when shift =>; c1 a! d6 a% [4 k' c
clkdiv_cnt <= clkdiv_cnt + '1';
5 G' { }7 b) a' v* s& ? if (clkdiv_cnt(2 downto 0)="111") then8 K. u/ l' z- L J/ M. u
sck_o <= not sck_o;- ~7 C% b# x" a# ]
end if;
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6 v% g# U& l" Y! k8 n! ]& W+ l if (clkdiv_cnt = "1111") then
# r& @& l& j: ?. b6 _ spi_o <= out_reg(13);/ i6 _9 q& C2 f1 N2 g
out_reg <= out_reg(12 downto 0) & '0';4 E9 l4 l: G- |/ |+ [# u2 V
bit_cnt <= bit_cnt + '1';9 H' k6 n5 n' A- F
end if;
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if (bit_cnt="1110" and clkdiv_cnt = "1111") then" D g; M/ |" R3 l+ Z) M
state <= stop;6 v$ ~9 j5 X4 E3 h/ Y
sck_o <= '0';- u# z; o. n* I! D% ?
spi_o <= '1'; |0 [; G- e* f7 \
end if;
+ s; a- M+ G6 y* a2 @# O 8 O/ Q9 O& B9 X! \# o6 L; }( [3 K
when stop =>
6 F9 c/ |# L* F* H$ Q% j8 K state <= idle;! C! ?3 h% J0 R, }- o- D2 E
sck_o <= '0';- c& N( m" H/ p7 ^, p- i! H
spi_o <= '1';
! R5 g3 b7 c0 Y! {# {9 L clkdiv_cnt <= (others=>'0');( l4 V* e4 i, ~& Z8 N$ l
bit_cnt <= (others=>'0');
, {& g& G; I& _ full <= '0';% E' j1 J+ e& Q( z: B+ `$ k
when others =>
7 @9 r# {( Y! D- h1 m' u state <= idle;
3 T3 u* J3 `0 k8 s$ c( B: v" ^$ B end case;
a4 @# Y# {$ c* ~' S" ^ end if;4 x$ C1 _0 V- g/ h
end if;) p5 {8 z! ^/ e2 Q
end process;
. P; c% ^, J$ Y8 s" G8 j6 L3 Pend b;! `5 K( f# M$ {+ @
$ F0 z' A. W5 R" L; G& ?6 R6 h q* f' {. o/ ` ~
其中out_reg 一直是0,在idle状态赋不上值,大家看是怎么回事
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