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DATE: 05-14-2010 HOTFIX VERSION: 008% R8 Z4 ?. S; V( B7 q1 `
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
& U m9 S' ^/ F===================================================================================================================================
" B* w; O; a1 G! @( k697699 CONCEPT_HDL HDLDIRECT SCM Verilog output contains the line 揹efparam <instance number>.SIZE# u4 V$ u8 a5 c! o+ a4 F
734169 ALLEGRO_EDITOR PLACEMENT Wildcard asterisk character giving "illegal char(s) in refdes entry." error in quickplace.
" ]2 W; q/ n T0 M6 `3 }' g738970 SIG_INTEGRITY GEOMETRY_EXTRACT power bus issue with SSN simulation when device is on bottom$ W- U! n3 o7 C& c( o6 ^8 E
744762 CONCEPT_HDL OTHER Connection dot sizes do not match on printout vs. screen# M5 ?+ }& d# n# |, t" a. i
750371 MODEL_INTEGRIT GUI Model name in physical view cann't match the model in right workspace5 z/ h; e- g, Y) M! L8 p$ Q
757024 CAPTURE STABILITY Capture crashes while exporting to EDIF
$ t7 l, H0 E6 T# F7 S) Y759094 CONSTRAINT_MGR INTERACTIV One member of a diff pair will show Analysis Failed when analyzing the design.+ R8 Z6 D: F/ Z1 k# N8 D% w
760178 ALLEGRO_EDITOR EXTRACT Crash Allegro when executing extracta command for big size design(size of .brd
/ C L. v1 [+ m3 }% M' z! I) k! `761391 SIG_EXPLORER OTHER Incorrect rise time
3 r0 K9 Y4 Z4 L" n( f1 h) {762402 ALLEGRO_EDITOR MANUFACT When photoplot(RS274X) of MM unit was loaded, shape was broken.' Z- E" O @. I/ x
762783 SIG_EXPLORER INTERACTIV sigxp - coupled tline on stackup layer should show solved impedance$ V! Q( \ b- M3 d" i% Q8 M5 o3 q
763150 ALLEGRO_EDITOR OTHER Request - IPC356 output truncate the padstack size to fit into the columns 59-62 and 64-67
2 [7 E, n; w# a763556 SIP_LAYOUT ASSY_RULE_CHECK Assembly Rules Checker is displaying an array of confusing DRC's on a Soldermask shape., L& Z' {( D& z9 N9 S, B' {; r! K
764399 SPECCTRA ROUTE Manually routed trace in Allegro are ripped OFF after routing in SPECCTRA using Route > Route Editor.! N- R/ V, J1 p0 x" W5 G
764475 SIG_EXPLORER INTERACTIV topologies from earlier versions cannot be opened in 16.2 on a machine
6 ?% B5 @5 K' z. c2 \0 p765287 ALLEGRO_EDITOR PAD_EDITOR attempting to open padstack fails with - database has a non-recoverable corruption.# }7 f5 E/ R' H5 v- `% @
766041 ALLEGRO_EDITOR OTHER Auto B/B via generator incorrectly defines some BB vias" B9 n; L2 C; A( F5 i* ^. Y: e
766153 ALLEGRO_EDITOR SKILL Allegro crashes when trying to extract padstack information7 `3 V; G: b& Y! ^% f
766611 ALLEGRO_EDITOR EDIT_ETCH slide creates DRCs in ARK area3 u. d0 m; y! Z4 `& k# q
767041 CONCEPT_HDL CORE The tap command failed because the specified tap body CTAP is invalid
4 q: a+ W9 u2 u" D# C7 @! K! n" ~2 C767146 FLOWS PROJMGR Project manager open last open .cpm in 15.7 version not in 16.3, ^$ D) r) O+ I( l' A2 R |" w1 T
767526 FLOWS PROJMGR Project Manager customization does not work
. H/ o8 |, C O3 E767671 APD DATABASE Crash creating cline with axlDBCreatePath() on this database.
9 C+ J7 p/ d: W: ]6 J767951 ALLEGRO_EDITOR DATABASE color net param file omits nets with bus brackets in the name U7 E! H! o1 G: o5 \ p
768168 CONCEPT_HDL CORE Fontsize on instances changes when doing backannotation5 _! O3 r$ }6 z! U
768207 CAPTURE STABILITY Capture crash while editing properties" { ]) I1 |9 j! ?/ i0 g4 g
768734 CAPTURE PROPERTY_EDITOR Properties of title block are not getting editted through spread sheet.
6 ^2 }1 c( f: d# X X" w768832 APD DRC_CONSTRAINTS Following Performance Advisor instructions results in much longer DRC check time.! m% _8 T* S, D+ v% v
768990 F2B PACKAGERXL RFSIP architect 16.3 85Y Schematic to SiP fails due to softinclude in cds.lib file this problem does not occur on 16.2# a- F" f- F/ d& s
769097 SIG_INTEGRITY GEOMETRY_EXTRACT Sip Digital SI-Bus Simulation function will shut down auomatically when it is running' ~4 i3 x: X( W1 p# f. v3 t
769235 SPIF OTHER need to be able to remove mbs_spif* properties added by mbs2brd! E' V g. ^. }2 S/ L6 u* N
769326 CONSTRAINT_MGR DATABASE Length by Layer crashing
+ s: O, i& ? \/ ^769336 ALLEGRO_EDITOR TESTPREP testprep density - returns Unable to add the PROBE_DENSITY subclasses.
( Q( O+ l a2 N& S1 _, S8 \769458 ALLEGRO_EDITOR OTHER SMD Jumper has a problem about the connection point when using the Add Jumper8 f4 s! |9 } R. g8 V _3 i3 Y( D5 k
769845 ALLEGRO_EDITOR EDIT_ETCH Diffpair routing out affected by line to line spacing rule.
% k2 Y6 Q* m# s/ @0 }$ ~( c769934 SIP_LAYOUT WIREBOND Duplicate Finger Name.$ Y% W$ M/ [" x4 U) b5 T' R Q
770006 ALLEGRO_EDITOR OTHER Ratsnest_schedule[Power_AND_Ground] can not show figure without move symbol.- ]1 L# w. s# F) X/ N
770125 ALLEGRO_EDITOR DATABASE PCB SI GXL Via Labels grayed out on formand labels not visible on the canvas
+ B$ E. o/ N# |) c" ]. v- q770212 ALLEGRO_EDITOR DRC_CONSTR Incorrect Etch Turn under SMD pad DRC error on this board
2 h% ]3 B( x+ a Y2 ~0 U' m) o/ t770230 ALLEGRO_EDITOR ARTWORK Artwork fails to suppress unconnected pads on pins with the net_short property.
% R- {4 n$ L1 w/ y, v2 b, b770233 ALLEGRO_EDITOR MANUFACT Fillets are not behaving as intended.5 J% \+ e" f8 V% h
770442 SCM PACKAGER Error during Export Physical - The subdesign block instances ares not updated with reuse properties
- _( m' m8 H- p; D0 _6 E2 B770556 CONSTRAINT_MGR ANALYSIS PCB Editor's Constraint Manager not updating custom constraint cell., j/ g/ Q4 u1 ?, X
770861 ALLEGRO_EDITOR PADS_IN PADS translation fails with no error message
0 f5 ?, [1 c4 E7 u8 \0 K770872 SIG_INTEGRITY OTHER Opening Orcad PCB Editor for this board takes Performance License as well; @( Z! P# j9 Y. e
771117 ALLEGRO_EDITOR DRC_CONSTR Allegro PCB Editor crashes on Update DRC-16.3/hotfix006
# y, f$ l! I. A- h' C8 {771181 ALLEGRO_EDITOR PLACEMENT Component deleted completely from board file after we Mirror and rotate them while moving them., j& K9 P9 L. O" Q
771256 ALLEGRO_EDITOR DRC_CONSTR Update DRC consumes system memory and crashes allegro after approx 30 minutes6 y* g8 v2 k4 k. H
771423 ALLEGRO_EDITOR SHAPE Shapes - Update to Smooth - Low on available memory please exit the program.' l( A3 X* O8 @" a
771456 ALLEGRO_EDITOR EDIT_ETCH Allegro 16.3 crashes when using arrow keys
) ?# T1 U4 `. M) Z/ Z/ F771719 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license.# c/ U) h6 q }2 e# l
771765 ALLEGRO_EDITOR PADS_IN PADS translation fails to translate symbol
& i: M, p( a j- E% Q0 O771766 ALLEGRO_EDITOR DRC_CONSTR Moving certain components takes a long time on this board database.) g8 \0 [: i9 S& I) ]; N
771815 SIP_LAYOUT IO_PLANNER SiP OA co-design flow does not allow a save to the .sip file after modifications in IOP3 S" X# h# [' `% X8 P
773072 SIP_LAYOUT ASSY_RULE_CHECK wire to wire same profile
; L' A# r( z; P8 t- A" w2 z773126 CONSTRAINT_MGR UI_FORMS Constraint Manager "Value Filtering" for Topology Schedule is missing TEMPLATE and "UserDefined") E8 I7 o- [& T) z. v- v( W! C6 _
773179 ALLEGRO_EDITOR PAD_EDITOR pad_designer crashed when attemting to delete internal name layer.! }) ^* P! A) A2 ~+ c$ ]
773229 ALLEGRO_EDITOR OTHER Netrev never end importing netlist generated from Capture CIS' j+ s1 C# s2 A7 x8 X/ `
773329 ALLEGRO_EDITOR MANUFACT Allegro closes when performing a Linear dimensioning and then selecting the undo icon. X R" l1 U4 w" f
773483 ALLEGRO_EDITOR MODULES place module problem
: T5 ~. {+ l8 K- F: \, O3 v774036 ALLEGRO_EDITOR INTERACTIV Rats not shown after move->mirror command( H" n$ ~% B: S: M1 r
774170 ALLEGRO_EDITOR DATABASE DBDOCTOR fixes Error but it reappears and Artwork fails
9 P' F& P( L5 {8 o. V774602 SCM OTHER ASA crash while working with hierarchy
' c2 f8 W/ r8 ~/ r, t7 y% ?+ W774643 CONCEPT_HDL CORE DEHDL crash on edit of attributes. r/ v, W* H9 i; j
775201 ALLEGRO_EDITOR SKILL Color palette can only be changed one time using skill commands' q0 N+ N! b( v0 X
775815 SIP_LAYOUT WIREBOND Unused wire profile once purged using wire profile editor are still available in CM and Color dialog' w# R/ Q1 m- |3 L: \9 D
775826 SIP_LAYOUT WIREBOND Cannot change the Wire Profiles on the wirebonds in this design
8 J. Q1 k$ S' S2 a8 D8 Y! i775842 SIP_LAYOUT WIZARDS Die text in wizard is changing DIE location when origin set in DIE text file is other than 0, 0& a2 \) x" D7 `9 m; F. ]1 w
DATE: 04-23-2010 HOTFIX VERSION: 007. j& b$ k* u+ M" g9 ~- b
===================================================================================================================================& V* y7 |! L( b9 j
CCRID PRODUCT PRODUCTLEVEL2 TITLE- B8 l$ n) r9 E3 W; @/ i( N2 O
===================================================================================================================================8 h4 \( N8 k8 ]
721859 ALLEGRO_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why?0 |# x( m- B9 C$ M
740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp
! x \. W: S, k3 B6 x! e$ ]744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools
/ n4 y' P) j- b" W& J8 b1 [! J0 j747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0.
7 z4 d6 @1 v4 m+ A( x747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash.5 S7 z0 ?; ^$ T4 M5 z- r
751372 CAPTURE OTHER Copy / Paste Issue in capture 16.3
. K2 n6 ~) w7 x0 J6 W" K9 x757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit.: H% A: [4 k# A% g# K9 c! Q
759906 CIS PART_MANAGER Property copy from one to several parts doesn't work1 T" B! l5 y2 E9 O
760154 PSPICE NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result
' |! ~/ E4 x0 w/ R761177 CIS OTHER Error Message - Memory exhausted
+ d* R8 ^% w: C: K, Q: r762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location.* k( m* Y. e( I
763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.$ [7 L6 F T6 ^0 `
763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created.
. u9 V q$ M* A5 e8 B) t0 O763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager?" s" k8 v! Q) e: W! i5 }
764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.3
& y2 @$ z* S5 g764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle.
& E5 R/ _- j: s2 j8 H764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad
: Z' P. t0 {" y764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.3% i' G! l6 l( d, g3 c! o
765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro" P9 c! z& o' y- O( i
765319 APD DRC_CONSTRAINTS Identical Constraints in Performance Advisor question) Y3 U" H# p$ ~
765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape.
$ z/ V" Y- ^6 p$ X766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle
x- I) Q" R, _766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design
8 v9 o6 N9 i5 Z3 M5 V3 u% q766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.3
6 ~- ~6 r! Y q2 t766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit
4 a$ |+ V; T+ g4 _" v( @' l767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version.
$ W2 e( H2 m/ d& g767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step.+ f% k6 H, E2 |* p9 ^9 Y3 [. A
767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs.5 Z2 K* r& k, } J* q% f
767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly
, |8 r n) O9 l4 [768822 ALLEGRO_EDITOR SKILL axlSetParam return value is divided by 10 to the power of the design accuracy.3 h8 T/ ]# }5 @ p" s
769150 CIS PART_MANAGER Update All part Status on a group changes 揇o Not Stuff?status to 揝tuffed?in V61.3_ISR_5.! z1 H+ p& T/ ]& q9 g. H
DATE: 04-09-2010 HOTFIX VERSION: 006
5 l- f$ \6 |0 C! ]===================================================================================================================================1 I. V4 T8 T: q3 }- Y i$ G4 k7 U
CCRID PRODUCT PRODUCTLEVEL2 TITLE& U# W- H/ |9 ^9 M( \
===================================================================================================================================
' ]% ^& Q, \/ i745241 CONSTRAINT_MGR TECHFILE Importing a tcf file automatically enables On-Line DRC.
: k5 \+ L2 C. Q752587 ALLEGRO_EDITOR PLACEMENT Uppercase File name(XX.mdd) for Placement replicate update on Linux.
. ?8 v7 I" s3 E0 x# v753626 CONCEPT_HDL CORE newgenasym error while saving the hierarchical block symbol. z2 {: B1 k; u$ t$ P
753894 CAPTURE OTHER Case sensitive version control S/W
, [; A; `9 M/ F( X5 ^4 W754487 RF_PCB OTHER Various asymmetrical clearance problems uncovered - calculation issues?. L4 n9 `6 M( n; `8 i6 [
758272 CONSTRAINT_MGR UI_FORMS Entering values on the Min/Max Propagation Delays worksheet hangs the application.9 d8 b3 r* K p) l8 @
758911 PSPICE PROBE Pspice crashes while exporting probe data using our sample project
4 m6 \7 g! @1 c: U5 l) j759871 CAPTURE PROPERTY_EDITOR Save option in Right Mouse Click on property editor of nets doesn't saves all the changes.; @' a2 K3 B) y8 d7 [* R9 m
759890 SPECCTRA ROUTE Specctra autorouter ignoring prerouted nets
! r! e5 e1 U( Y3 y; h* ~! b760067 ALLEGRO_EDITOR SHAPE Dynamic Shape not getting filled on board with odd angle placement and routing( q$ [, t) C- D, c. n+ f; t
760284 CONCEPT_HDL CORE Update Sheet Variables turns of the grid. X/ l' K! b% W
760480 MODEL_INTEGRIT OTHER Message open clipboard failed when trying to open the rename/reorder dialog in Model Integrity
u& i9 ?3 y+ d0 o760667 ALLEGRO_EDITOR PADS_IN The pads_in.exe translate incorrect drill shape from PADS 2005 ascii database.
% X7 `& o% } i760741 ALLEGRO_EDITOR MENTOR mbs2brd does not work in 16.3 but works in 16.2
" {6 v, x9 `$ U |760810 CONSTRAINT_MGR INTERACTIV Deleting Region Deletes NCCs7 k \/ Q& P7 r
761114 PSPICE PROBE Refresh issue in Display > Cursor window% I8 O/ G8 P, z. p2 S! J! o
761180 ALLEGRO_EDITOR DRC_CONSTR Via_at_smd not working for custom shaped padstacks.: [- ]1 K& J' e; |$ t
761305 SPIF OTHER Allegro crash when seleting any of the Route - PCB Router - submenu items.
1 z' `/ a! ]" Q. C( z. Z, }8 f. \761376 ALLEGRO_EDITOR PAD_EDITOR Wizard_Template_Path is not considered for symbol template look-up ?! z/ P' L, H& l, E6 o; @
761416 ALLEGRO_EDITOR DATABASE Allegro crash on chaning the subclass for group of clines
Q1 {5 L: y- s d) f. }761492 ALLEGRO_EDITOR SKILL about axlTransformObject function. W7 K& n5 _4 ]( a4 v" Y, Z
761518 F2B PACKAGERXL about mismatch library path between cds.lib and actual
}' h# a& s0 A% ?1 n761737 ALLEGRO_EDITOR OTHER Running Dbdoctor after executing Skill is giving symbol fit error for the .dra file4 ]* i' g7 t2 K" `) X
762155 ALLEGRO_EDITOR SYMBOL Updating a symbol changes the netname of the cline resulting in drcs.& i: E1 ~" g( L9 F
762181 ALLEGRO_EDITOR OTHER Allegro netrev crashes for long device name in PST* files5 i/ e n4 ~+ `- G
762316 ALLEGRO_EDITOR MANUFACT Allegro disappears on Adding dimensions for the symbol file
/ S1 v5 S) @& h9 Z0 F762792 ALLEGRO_EDITOR PADS_IN PADS_IN fails for SPB 16.3
7 V) K6 e* [; I763108 ALLEGRO_EDITOR SHAPE Z-copy shape create an error like VOID boundary may not cross itself( V) B" m5 M: I5 x6 q& M
763134 SIG_INTEGRITY SIMULATION Bit 7 of a simulation is out of sync with rest of bus. It should be the same for all bus values.
: m5 d4 M% L6 q763149 CIS GEN_BOM CIS BOM in V16.3 is not correct if database has Quantity field and its value is 0. V; J1 T z& E
763296 ALLEGRO_EDITOR REFRESH The error was happened while doing the SUM
/ R. y; @/ f" h* g7 c763303 ALLEGRO_EDITOR OTHER SMD Jumper has a problem while using the Add Jumper2 O$ T3 X0 l; ~
763315 ALLEGRO_EDITOR PADS_IN pads_in got error message WARNING ERROR(SPMHDB-205)$ @; `& v/ r, i% L9 y
763354 ALLEGRO_EDITOR PADS_IN Auto suppress redundant shape while using pads_in translator
* h# Q1 R# ?4 k763428 ALLEGRO_EDITOR PADS_IN enhance pads_in.exe translate spacing and physical rule into Allegro.7 Y* ~, b. t9 H, W$ v* N1 i
763446 ALLEGRO_EDITOR REPORTS missing fillet is reporting pad without drill. V3 b8 o, M F! H1 m2 n' U6 G
763448 ALLEGRO_EDITOR DRC_CONSTR Performance advisor shows Cset as unused nets when it is assigned to Diff pairs or xnets.
! \! N1 |" Y8 q6 M763586 ALLEGRO_EDITOR DATABASE Allegro rounds off the value after decimal in CM: X2 k" H! Y0 g |
764077 CONCEPT_HDL CHECKPLUS The output predicate in the Graphical environment is not always returning the pin object for an output pin.
+ c) H6 T) d+ _: F6 q) S3 ]DATE: 03-26-2010 HOTFIX VERSION: 005. O$ Y3 e2 L6 h6 E: `, F
===================================================================================================================================0 D; @8 }1 o! U1 q0 {
CCRID PRODUCT PRODUCTLEVEL2 TITLE
E( S2 R+ W- \0 L===================================================================================================================================# b7 f: J' J) o- Y) u
599819 SIP_LAYOUT 3D_VIEWER display soldermask by default in the 3d viewer
% h- }% v7 `' \# h735992 CONCEPT_HDL CORE Create Test Schematic does not use the correct package type3 H* I3 g+ v, u3 Y5 \7 {# `" [/ D
743787 SIG_EXPLORER OTHER 16.3 SigXP crash if sigxp.run created by previous version exist.7 B$ B! r+ u" |0 E3 \
746320 CAPTURE NETLIST_ALLEGRO Remove Semi-colon from invalid pin-name check during netlisting
5 x+ L9 w+ |. O3 ~' h: } [* D4 O746444 ALLEGRO_EDITOR OTHER show element fails to display info on a via if it is in a module./ j- P# {: o- A; {4 o
746726 SIG_INTEGRITY SIGWAVE Save As and Open Dialogs open in last saved directory
8 {+ O% K3 g) V% Z3 S! ?# N750080 CAPTURE NETLIST_ALLEGRO Improve error message ERROR(SPCODD-390)
" g% `+ H1 _( a1 t1 E750606 SIP_LAYOUT ASSY_RULE_CHECK Wire to BF same profile check
2 [, f; ~9 ]; A7 Q: G751492 CAPTURE FPGA Option to swap the pin-numbers rather than their locations in the Schematic after back-annotation
8 g# G9 ~; r- `' G- Z753834 CIS LINK_DATABASE_PA unable to link multiple database part8 u* O. R3 C$ M3 n3 v
753990 F2B PACKAGERXL Delay in opening the subdesign tab in the Export Physical setup in SPB 16.3: B2 f, r! R% ^, J
754328 LAYOUT TRANSLATORS L2A gives error Subclass name TOP not valid Allegro subcls with s029 hotfix
0 j+ ~6 H* l( M k2 r2 D754434 CONSTRAINT_MGR OTHER allegro crashes when deleting matched group) R$ L& g* M2 m6 j% F$ V) ^: Q3 a+ x
755111 ALLEGRO_EDITOR INTERACTIV "ALT_SYMBOLS_HARD TRUE" property does not work when I mirrored symbol using move command in 16.3.& i' A1 z4 r5 Q- k- G* [
756131 PSPICE SIMULATOR Capture crashes while re-running simulation5 k9 t, f/ j2 u
756148 PSPICE PROBE Zoom Area in Probe Window does not work for digital signal in SPB1634 Q+ c# I1 n4 Q; M
756169 SIG_EXPLORER OTHER Signal Explorer crashing due to sigsimcntl.dat
7 _: l7 i/ l$ R0 t* w( |9 [756176 PSPICE PROBE Trace color is wrongly interpreted in PSpice probe window.
3 K6 e( x6 \4 W* q756224 SIG_INTEGRITY SIMULATION Simulation aborts reporting that VIA models have changed
' x# G) k7 O: @756281 ALLEGRO_EDITOR OTHER Why *.sav file cannot be recovered from PCB Editor utilities?
- Y. B( x% g1 ^8 T4 ~756673 SIP_LAYOUT ASSY_RULE_CHECK Running ADRC Metal to metal checks causes false X-D DRCs, cannot clear them and trying crashes the tool
+ S$ a- U/ s% z/ P- v# f756918 ALLEGRO_EDITOR OTHER Allegro angular dimensions working incorrect in 16.3
# \' Q6 F) k- C8 l5 Y/ \6 l$ V' q756932 ALLEGRO_EDITOR CREATE_SYM Create symbol fails with error duplicate pin number; L# e, g* S. P$ t0 ^8 Q
756976 ALLEGRO_EDITOR SKILL axlChangeWidth always return nil in Allegro version 16.38 }% i v) h( t" u3 I# [; o) {& j' _
757000 PSPICE NETLISTER Incorrect Hierarchical Format Netlist created( V u9 ]9 [: k, W
757406 APD OTHER Implement Segment over void features in APD L
+ |5 U* c2 [ ~1 q6 h& e9 ^757624 SIG_EXPLORER OTHER Sigxp runtime error when simulation is run and exit without saving the topology
- K: o: r' g) `* z @# ~4 T757820 ALLEGRO_EDITOR SHAPE Shape does not void to hole if there is no pad
9 p/ }+ q4 b" k758009 ALLEGRO_EDITOR OTHER Export > Library (MECH_SYM) adds a new subclass NCROUTE_PATH, data moved from one subclass to another.
. j9 O' G1 M3 N5 K758022 CAPTURE DRC Capture crash while running DRC with 揜un Physical Rules?checkbox.$ G$ _4 r5 H# r4 C
758190 ALLEGRO_EDITOR PAD_EDITOR PCB Editor crashing on pin move in this design0 u! K' Q1 v/ }
758374 F2B DESIGNVARI Problem with Mechanical part in Variant Editor
9 l! y. I1 f$ C758471 SIG_INTEGRITY OTHER Differential impedance does not change on changing the etch effect values.
5 z B+ Q% I1 v758490 CIS CRYSTAL_REPORTS Different crystal report output in 16.3 than from 16.2; V4 z; e4 M0 ^/ N6 d
758498 CAPTURE NETLISTS PCB Editor netlister hangs
' |4 T& n% Q1 R( z; W6 q758584 APD SHAPE Shape not voiding all elements
" m: F$ `) B" W6 i* ?% j0 ^758886 ALLEGRO_EDITOR REPORTS Total number of nets is wrong into Testprep Report
. ]4 ?! k5 Q4 {+ q759146 ALLEGRO_EDITOR SKILL The title is not displayed in the form by the version.
2 c, J) k% B+ c6 ~8 M759339 ALLEGRO_EDITOR ARTWORK artwork output fails by SPB16.x.& i/ d0 Y; c7 x) V/ L, q% ]) L
759591 ALLEGRO_EDITOR SKILL axlSetParam fails and does not round the value as indicated by the warning message
8 p+ J, j5 U2 _7 k: Z759816 CONSTRAINT_MGR OTHER Allegro Hangs when double click on a Bus in CM4 H2 Q& i; ~. c
759947 APD OTHER Need an a way to convert Lines into Clines/ u5 k% i& \8 Q0 H9 h
760353 ALLEGRO_EDITOR MANUFACT Allegro crashes and creates a .sav file on running the silkscreen command from Manufacture > Silkscreen% j! X, W: y% Y. r$ B- `
760432 ALLEGRO_EDITOR PARTITION Unable to remove fixed property after partition import
( n! J% b) {" N2 z760638 ALLEGRO_EDITOR PADS_IN pads_in translator can not handle " PINPAIRGROUP ".: U& {3 z) S( b- r5 H+ ?) P
760734 ALLEGRO_EDITOR SHAPE Different therma contacts on rotated partsl0 X( u! R7 y& ` s# w4 u; E4 Q! }
761436 CAPTURE NETLIST_ALLEGRO SPCODD-53 Error when creating netlist with PACK_SHORT( T7 n8 ^; }) w$ {2 S- r
DATE: 03-12-2010 HOTFIX VERSION: 004
" }" @+ r% G: j' h @+ j6 H8 E===================================================================================================================================9 @% L2 }+ G: K0 _) g3 U J3 `
CCRID PRODUCT PRODUCTLEVEL2 TITLE0 N |: ? Z8 w* r. G
===================================================================================================================================7 }! `! [4 v7 E4 z1 I9 k0 u6 B
689495 ALLEGRO_EDITOR DATABASE corrupt database
`8 v6 D" |0 p, F0 ^725944 SIG_INTEGRITY GEOMETRY_EXTRACT xtalk make allegro freeze and never give hands
: B% O6 V6 G, C. K732604 SIP_LAYOUT SHAPE Shape Issue - added shape will not clear around other elements.7 o/ t" B' z% a4 O0 [$ ~: P& V% c ?
740106 PSPICE NETLISTER The "Enable PSpice AA Support for Legacy" option does not give the Desired Monte Carlo results: k2 D! ~4 v0 N! g. r
744259 SCM UI Signal order reversed when a Vectored Signal name is renamed in reverse" L" a7 R% _1 ?
745554 SIG_INTEGRITY GEOMETRY_EXTRACT Time to get Xtalk simulation result in 16.2 is lower than acceptable by comparing the time in 15.7
/ \% U8 c9 w3 Y8 c! I745595 RF_PCB FE_IFF_IMPORT import iff RF_PCB give an empty block
) i% ?6 F* L8 E0 \747133 CAPTURE STABILITY ERROR [DSM0006] Unable to save# [1 Y. F/ T5 o9 G
747679 CAPTURE STABILITY Trying to Save the Design in 16.2 format gives DSM0006 Error and crashes Capture
5 ?& [" N! X t( S" h0 Q750460 CIS FOOTPRINT_VIEW 3D footprint viewer doesn't shows the footprints8 [* C0 G0 p5 V, X. u
750777 SIG_INTEGRITY OTHER Trace impedance showing wrong4 B- x- q( J. R" g1 _
751424 ALLEGRO_EDITOR DRC_CONSTR Unexpacted DRC for Shape to Route Keepout
# c# \+ i2 C9 `2 p* K& i751897 SIP_LAYOUT SPECCTRA_IF Radial Router crashing SiP tool
$ h3 ~; u$ @9 N3 L- V1 z752029 SCM OTHER Cross probing not working between SCM and Allegro Editor in Linux Environment4 `2 b( H+ q# s
752450 APD PADSTACK_EDITOR APD crashes when selecting a User Definable Mask Layers.
" z! M7 @) S3 J9 n9 ]- Z; h3 V' H% d; s752581 PSPICE PROBE Pspice probe window crash
; Q D# Z! d- R7 x# j3 ~- |752709 ALLEGRO_EDITOR PLOTTING Sheet content doesnot plots title block
( c4 G7 }) g$ d: C. N1 x752908 ALLEGRO_EDITOR INTERFACES Output from Export > DXF shows one instance of a via on the wrong layer+ ]: P* I& L$ @ n+ D
753226 ALLEGRO_EDITOR OTHER File > Change Editor doesn't shows the default Product Options
2 V3 b$ Z5 U$ N) W+ |4 M* Z5 B753622 ALLEGRO_EDITOR GRAPHICS Enahnce capture image command to default the save as location to working dir6 R/ {( ]& n5 j1 U4 R, _
753773 APD WIREBOND Requesting the option to set the diameter of the default WB_TACKPOINT power ring pad.. h8 B9 `$ ~6 o% w& v
753778 APD IMPORT_DATA Import NA2 displays the design momentarily and then crashes5 Y( U1 c1 v; t: n; p6 R, U
753866 SIG_INTEGRITY OTHER about Select by Polygon after move command/ k7 j: G: D- \8 j
753958 CAPTURE OTHER Capture V16.3 is extremely slow while edting schematics of design placed on network drive via VPN.
+ Q+ ]" U) j E5 @; q. m* w754050 ALLEGRO_EDITOR UI_FORMS Why show element window disappears when scriptmode is set invisible! L) m7 E! x% u0 Y
754143 SIP_LAYOUT OTHER SiP Package Design Integrity - running Extra Cline segments generates report without Layer number
# T. ~4 U7 o" ]) q754327 ALLEGRO_EDITOR OTHER Rename Sub Class is not working as desired.
: {) v: P8 i( Q- f; f% }' ~( }754364 ALLEGRO_EDITOR PLACEMENT Crash when applying placement replication
( P1 c* Z9 e' i754462 ALLEGRO_EDITOR SHAPE Allegro circular dynamic shape fails to fill
" c# k3 a; F% N& F) I754819 ALLEGRO_EDITOR OTHER Create details shows wrong graphics for filled curves) ?# R, D. O% G( ^. Q# r8 e- M
755176 ALLEGRO_EDITOR PADS_IN Pads translation succeeds in v16.2 but fails in v16.3 on this ASCII file) h: ^) ]$ `2 @6 K1 l$ H
755256 ALLEGRO_EDITOR OTHER Attached script is crashing the designs in v16.30 k9 Y4 N# _1 b* K6 X7 ]3 `5 [
755610 CONCEPT_HDL CREFER Cref hyper links does not work for signals where number "0" used to define the zone for page border0 o- d* c% v" h1 d/ R
755787 ALLEGRO_EDITOR EDIT_ETCH crash using resize_respace_dp command g% f( I3 I; A n
755881 ALLEGRO_EDITOR DATABASE Swap component crashes application
^) x( _; ^. i: j756092 CAPTURE PROPERTY_EDITOR property editor flickers and loops on value edits
, j2 H$ p4 n/ H4 Q$ M. wDATE: 02-23-2010 HOTFIX VERSION: 003" a" r! Z4 T0 J0 `- a: @
===================================================================================================================================
8 O8 w' E$ O# A" s0 C+ V1 G) ?# q" vCCRID PRODUCT PRODUCTLEVEL2 TITLE5 @0 e& t. J" p& }/ w* R7 t( _6 ?8 n
===================================================================================================================================
( R$ n; O% [; e$ S2 r$ I0 i, |$ t) k263504 CONCEPT_HDL CHECKPLUS Checkplus fails to run if crefrpt exists in the design
5 _$ h# G+ C+ i! T9 e0 N726836 ALLEGRO_EDITOR SKILL axlGeo2Str() and axlGeoEqual() return different results& z, Q6 S% v2 r z- }. W
730820 SIP_LAYOUT PADSTACK_EDITOR Changing the Via diameter will cause the SiP tool to crash
, D1 b9 D9 b7 n6 D) I735193 CAPTURE FONTS Pin_names and Pin_numbers get convertred into darkened blocks in 慫oom to all?view in V16.2.6 Q( v" k; a3 d d+ @
737307 SIG_INTEGRITY GEOMETRY_EXTRACT differential pair extraction to sigxp fails to extract coupled sparam via models
& S# N# ?8 v: b, w740936 ALLEGRO_EDITOR SYMBOL Confusing error message during Create Symbol
" O" C8 _4 b$ {; Z) y- _744191 ALLEGRO_EDITOR EDIT_ETCH Arc routing enhancement
% ]6 p- i9 e% u2 y+ g6 M744497 ALLEGRO_EDITOR INTERACTIV PCB Editor Crashes with Data Customization Feature
# _* I4 h' P; E; p; U7 t746572 ALLEGRO_EDITOR DATABASE Reoccuring error in attribute pointer to attribute invalid on dra.
4 Y" b# Y' M" c- |0 }746978 SIG_INTEGRITY SIGWAVE 2 licenses were used for SigXP and SigWave./ S: M' |0 V$ h- f
747219 SIP_LAYOUT SHAPE Dynamic Filleting not working with odd angles
8 \. y- D9 D1 u. i6 S9 ^% U6 I$ v747593 ALLEGRO_EDITOR PADS_IN Some RULE_SETS cause the PADS translation to fail.8 c8 C" T; i6 Q) n0 F
747746 ALLEGRO_EDITOR OTHER Request for more detail in downrev.log file3 I( x5 O- Z1 b, {7 ]& D& N: U
748033 GRE IFP_INTERACTIVE Enhancement in GRE where Show Element on Bundleshould show the total number of nets that are part of the bundle
, _* K# J/ Q! f j L6 t" e6 f748333 ALLEGRO_EDITOR OTHER place by schematic page number not showing pages correctly
# @1 n- Q7 h: P" {# U4 c: h7 u748375 ALLEGRO_EDITOR MANUFACT gloss - line smoothing causes crash# A+ i5 k6 |: t% }
748818 ALLEGRO_EDITOR DRC_CONSTR Undesired DRCs shown in allegro 16.3 while moving component and the same are removed by update DRC8 t5 Q3 d4 @8 S. W
748865 CONSTRAINT_MGR OTHER Allegro 16.3 slow to move component with CM open( K' w) z- v! P0 t$ L
749009 APD WIREBOND a part of function of the finger alinement doesn't work0 A0 k7 B. k' A, P! @
749162 SIG_EXPLORER INTERACTIV Unable to proceed after RMB > Preference > Cancel
/ |* G/ p# W) E: f! J# O749307 ALLEGRO_EDITOR MENTOR mbs2brd fails with error VIF_Allegro_Write
- R O9 V3 i) o& z( O749435 CIS DESIGN_VARIANT Cannot create variant part in 16.3, c. z" U5 P( S1 V5 |6 g$ C# @- i
749854 APD PADSTACK_EDITOR The value of user-defined mask layer is not retained in the design.# M; L+ L& j1 V! c7 Q. j8 m
749891 ALLEGRO_EDITOR PARTITION Unable to delete existing partitions
# D2 \8 u: E5 L! J! c749949 SIG_EXPLORER EXTRACTTOP A Topology extraction fails using APD and SiP series with the latest hotfix(SPB16.30.001).
8 r1 K! J4 Y9 r# G! O750008 CAPTURE NETLIST_ALLEGRO Netlist different in SPB 16.3 and after installing SPB 16.3 hotfix 1
@) P2 O% z* t3 B! \750591 ALLEGRO_EDITOR DATABASE Analyze diff pair object fails to display uncopled lenght values.2 v- s7 O4 c! ], O
750888 SPECCTRA ROUTE specctra is crashing while routing I4 n4 \- K, T& F9 _. X6 J( @
751204 F2B DESIGNVARI Design difference crashes while reading funcview
% ]0 ]/ N9 I; L: }; [; I7 A751398 ALLEGRO_EDITOR OTHER Allegro Crash when Edit is selected in Setup > Outline > Room outline3 _6 ]# x ]: w: T. Z8 k! Y! L
751578 ALLEGRO_EDITOR PADS_IN pads_in hangs while conversion2 `- ~! M) I1 o7 l8 t
DATE: 02-09-2010 HOTFIX VERSION: 002
# A$ L. t7 N) \5 G===================================================================================================================================
; Z" c# u0 i% a( B% L" v9 X- LCCRID PRODUCT PRODUCTLEVEL2 TITLE
" }, D/ r7 ^" L$ a: R9 B( j( t===================================================================================================================================
1 D6 J5 u; Z# X527012 SIG_INTEGRITY IRDROP Severe Memory leak in IRDrop
3 [. V4 I3 ~, E7 z2 E5 _623678 PCB_LIBRARIAN CORE PDV freezes when changing grid
. M9 I9 U% E: }, K, S5 E6 v672592 ALLEGRO_EDITOR SHAPE Shape does not void correctly untill a clearance oversize value is added
% y! X- g+ L/ r6 q688062 PCB_LIBRARIAN CORE PDV Strange characters appear when copying text into Bus Arrows ( Text symbols)! n/ J+ S' d2 r& i9 P0 o
710170 SIG_INTEGRITY IRDROP Run IR Drop even if all components on the net are not placed.
# r* R. ~* Z% Y; g710174 SIG_INTEGRITY IRDROP Audit function for IR Drop.
+ M! ?6 w2 J) ^2 K; o726833 PSPICE DEHDL Modify the methodology for migrating 15.7 and 16.2 users of ConceptPSpice
: N# O X! g0 G( A( c730717 SCM UI Unable to delete a zero connection signal in SLP which has a pull-up
- y( V) n( E5 C731017 ALLEGRO_EDITOR DRC_CONSTR DRC's show out of date when artwork is run
: ~+ Y9 ?8 P. e+ i7 j0 }732145 CONCEPT_HDL OTHER Incorrectly generated VHDL netlist
' Q9 K: r0 H/ ?1 t q) B/ D0 f0 _740123 ALLEGRO_EDITOR GRAPHICS Capture Image command fillin missing from jrl and script files, i( I/ Z3 Q% c
740278 ALLEGRO_EDITOR OTHER Jumper fucntion for Single Side PCB Design. p2 K- X( {/ ?6 y0 @
740656 ALLEGRO_EDITOR GRAPHICS Can we place custdatatips.cdt file on a site level for SPB16.3) t* C/ A' T' Z& y
741222 CONCEPT_HDL CORE Replace command (in Windows mode) causes crash
6 S% T& b. g. [6 Q, q742389 ALLEGRO_EDITOR EDIT_ETCH Change or add message when using Countour route
2 x6 ~) Y, b9 H( C9 B0 Q+ ~743275 APD DATABASE With DRC enabled, this design seg faults in axldbid.c (solaris only). DRC update takes orders of magnitude longer on sun
+ L, Q2 K- I7 O1 j743623 F2B PACKAGERXL Pxl error when using pack_ignore on reuse blocks9 \4 w5 j4 V" Y$ o. p
744348 F2B BOM PART_NAME column getting word wrapped inspite of sufficient space in the HTML BOM report.+ T' {6 g/ @6 e2 \$ C
745062 CONSTRAINT_MGR OTHER import techfile does not add new layers in cross section5 A% _! B, Q, p7 s* I4 b- `7 B
745148 ALLEGRO_EDITOR GRAPHICS Allegro ptf driven HEIGHT value not pushed into 3D Viewer
& L, p. f9 E, i) a' `; d2 @( v5 K+ {745301 ALLEGRO_EDITOR DATABASE Allegro 16.3 crsh on moving component
# H5 a L+ ]8 T745518 ALLEGRO_EDITOR DRC_CONSTR DRCs not shown when "Enable Antipads as Route keepout is checked in"
8 o8 K' F& i/ u745745 SIP_LAYOUT WIZARDS Die Text In changing the pin names on duplicates/ t) \3 V v- H& E4 w& o
745785 CONSTRAINT_MGR UI_FORMS Unnecessary window opens when the cell in PCSet By layer worksheet was clicked.
4 a6 |" }5 Y4 I, i746002 CONCEPT_HDL CREFER Could not find pc.db in the root design
% k8 I2 R, X, u9 b- o/ f746010 CONSTRAINT_MGR SCHEM_FTB Updating the brd file using the "Import Changes Only" option overwrites the modified constraints in ~& n1 `) P; x9 x4 w8 B. q
746080 CONSTRAINT_MGR OTHER Click Constraint Manager filter icons crash software6 _# `2 u- W. u; h/ O* J7 D8 _
746137 APD IMPORT_DATA Import > NA2 not transalating certain layers and padstack sizes+ h* R; v5 F% u4 f" c1 ]
746370 ALLEGRO_EDITOR GRAPHICS Setting infinite_cursor_bug_nt variable flips mouse movement on flip design# A( ?3 f3 Q3 }1 L9 h( U8 ?& K
746519 CONCEPT_HDL CHECKPLUS CheckPlus the if statement is not seeing the True condition or the output predicate is not returning the True condition.! v/ u6 a- B& q0 } v5 g
746546 PCB_LIBRARIAN VERIFICATION con2con choosing incorrect PART_NAME in PTF File during verification
! b$ a0 F' L {& h746865 CONCEPT_HDL CORE Tool generated pspice net names in core concept design cause short with copy all.8 f4 Y* u: z9 `1 z$ x* z6 U/ D2 f
747636 SIP_RF OTHER RFSIP Layout RF Module Export chips & connectivity is not writing die attach method to chips file
z) f O. Q0 c, |. r7 TDATE: 01-31-2010 HOTFIX VERSION: 001
0 B% N" x) F* b8 T$ g0 ~===================================================================================================================================
% ?. l5 u0 ?0 [& nCCRID PRODUCT PRODUCTLEVEL2 TITLE
4 Q! q# ^0 A* p; E===================================================================================================================================/ x* f6 N W# O \1 A
491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute B) |; N; L6 f4 A4 b
496910 CAPTURE NETLIST_ALLEGRO Inconsistent netlist creation: L: Q& a7 z/ }% {
558783 PSPICE NETLISTER Why do Models with "awb*" prefix need wirte permissions to "*.ind" files?
7 i9 i( N& D2 I4 [643241 CAPTURE SCHEMATIC_EDITOR OrCAD crashed while replacing cache- J5 m2 z6 u" U6 s) p0 ]
654292 ALLEGRO_EDITOR DATABASE Propagation Delay constraint behaves differently between 16.01 and 16.2) ~7 l8 F* K+ e/ U
662829 CONCEPT_HDL GLOBALCHANGE Global Update should honor property visibility settings in ppt_optionset
4 U4 u3 \1 y1 k1 o9 F; T; t$ }2 I& n672718 SIP_LAYOUT EXPORT_DATA "Export>Symbol Spreadsheet" should export a .cvf not a .txt2 R% y5 }: d" x; k
676233 CAPTURE NETLIST_ALLEGRO Cross probing stops working if design name has dots, Q9 N/ s% K6 h. A% L/ T
678739 CONCEPT_HDL CONSTRAINT_MGR Manually added targets in matchgroups lost when reopen CM
2 z' b% `. S: X2 m" I4 l, m, \690618 F2B BOM Write protected template.bom fails to write callouts. {+ y( u1 z; U
700246 CIS LINK_DATABASE_PA Need option to update symbol always when linking part in CIS3 C: J' Z0 L2 M5 z
705393 CONCEPT_HDL CORE ConceptHDL crashes while switching to another hierarchy level under File > Plot Preview.
. j* ~ p( n' x3 d4 f708634 ALLEGRO_EDITOR SHAPE Shapes getting incorrectly displayed in 16.2+ x3 D4 l( K2 ~ }
708950 CONCEPT_HDL CORE Tool crashes while trying to change the text on the schematic using a text editor.6 u2 T% D: i) @% @
709823 ALLEGRO_EDITOR OTHER Arcs not converted properly when upgrading symbols
% X8 @% k6 r/ Q$ k0 P$ K+ B713964 F2B PACKAGERXL Net property Probe_Number is getting changed during the packaging run
8 y' p- F1 m; _/ D6 U) ^9 B718119 F2B BOM Exclude the callout file name from the template.bom file
. v: k4 }. l: `- g" z! m- H& S' y h718496 SIG_INTEGRITY SIGWAVE Frequency at smith chart.7 F8 ^ P0 o5 k9 ?
721422 CONCEPT_HDL CHECKPLUS Checkplus fails if "\\" character is used in the parameter list
; s1 k& a% X c: G. i( E721788 SCM OTHER SCM unresponsive while closing out a Block without Saving' w- a+ x5 D: Z* [1 G
721801 CONCEPT_HDL CORE Save As crashes DE HDL if an existing page is selected in the design
' R. }# C* X; W9 e$ C722653 F2B PACKAGERXL Packaging does not complete, f; @( u; y0 @, U6 v& v' F* p2 ^4 U \" F
725285 CONCEPT_HDL CORE nconcepthdl does not work same as concepthdl for same script.
* s. [/ B9 }6 }725719 CONCEPT_HDL CORE wire pettern of Publish PDF
1 v1 I) s( r1 g/ ~# m" R727062 CONCEPT_HDL CREFER Custom properties not visible for TOC symbol in schref_1 view
# \- U! h4 n( R4 F6 G' G727194 CAPTURE CORRUPT_DESIGN Random Capture crash; m- e n, V/ _" N
727704 SCM PACKAGER ASA to PCB getting out of sync8 X# A' R: |+ k! C% S
728066 CAPTURE NETLIST_ALLEGRO Allegro PCB Edtior net cannot be generated if PACK_SHORT is used1 D8 `* y2 w2 P+ L
729214 CONCEPT_HDL CORE SHOW_PNN_SIGNAME directive used with Windows Mode gives crash
$ k4 a2 ^- [7 f$ P: C' X730295 SIG_INTEGRITY OTHER Filled rectangle shapes not extracted properly( p5 l, O. L% z0 d: P+ w
731183 CIS QUERY_DATABASE CIS Query fails with ODBC Error for query (Price contains 29)
2 o) c+ T% Z8 a) n732073 SIP_LAYOUT DXF_IF DXF_OUT generate an incorrect shape3 g$ ~7 F' l0 j5 e
732138 CONCEPT_HDL CORE Cannot change SI model assignments5 @! I; C0 H4 A0 H2 I5 ] q" N0 f
732216 ADW DBEDITOR dbeditor crashes doing copy-as-new into lib folder that has partially completed chips.prt file$ S( v$ B) J0 D9 S& t! f
732249 SIG_INTEGRITY SIMULATION Probe sim with custom stimulus cause segmentation fault. Linux only.5 v- W+ v$ u7 j& F5 g. G
732847 ALLEGRO_EDITOR DRC_CONSTR Manual Void uses Shape to Pin constraint to void Holes0 U9 D- b" Y4 \# R
733261 FLOWS PROJMGR Project manager does not work with the Restricted User in client server environment( C! \$ g# r1 D4 |7 p" [, g4 R/ T
733773 CONCEPT_HDL OTHER Syntax issues in DEHDL
% C8 v E) t# }- n734260 APD COLOR Why subclasses still remain visible even after global visibility is turned off. x) s6 A, N/ ]9 U* h
734419 CONCEPT_HDL CORE Concept crashes in windows mode when netname is deleted on schematics generated by ASA5 E# h3 n1 m, }2 N. m/ V, i N: t
734555 CONSTRAINT_MGR SCHEM_FTB Import Logic does not overwrite the Constraints
& c# k, m4 Z1 z. j735290 CONCEPT_HDL OTHER Concept's PDF Publisher has issues.7 N9 |+ l* e, F" H3 J
735892 CONCEPT_HDL CORE "Component Modify" changes visiblilty of Key properties
# d5 J' e7 p! P7 m735977 ALLEGRO_EDITOR MENTOR Mentor to Allegro translation fails without any error message
" Q7 Y3 b0 h! J; u q, Q$ Q736071 CONCEPT_HDL CORE Property visibility is not retained on the schematic instance when we modify the component on sch.3 p# y; D* Q( q1 K$ S( J- n
736165 SIP_LAYOUT SCHEMATIC_FTB about error message of "schematic to layout"
8 @1 W: ?# L4 Q6 Q, K/ P736167 CONCEPT_HDL CORE HDL crashes when I select BGA symbol in Component Browser% C& n1 t' d, l$ H7 F( I+ o
736911 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge
+ y# P+ p/ I& v$ G0 E% m9 Z738035 ALLEGRO_EDITOR OTHER Measure function has different result between 15.7 and 16.2 version.# @: b5 r* v; }7 E8 K
738129 CONSTRAINT_MGR UI_FORMS Need Diffpair Constraints option in Analysis Modes Electrical Options with Performance license/ A i" Z. z- v, B4 l5 G1 d
738276 ALLEGRO_EDITOR PLACEMENT No feedback in console window when placing unfound components in Allgero 16.3
4 R) g, C2 U p0 Y6 M4 a- D) ^# F738366 ALLEGRO_EDITOR GRAPHICS 3d viewer not showing some connectors with mutliple place bounds correctly
8 Q5 O, |$ a$ K2 ^738454 SIG_INTEGRITY FIELD_SOLVERS EMS2D extracts incorrect CPW to Trace spacing( M; N" p0 q7 D! z
738578 ALLEGRO_EDITOR OTHER scriptmode +w doesnot work on Linux
) k: o i9 u. Y738869 ALLEGRO_EDITOR OTHER Error msg when cds.lib contains missing SOFTINCLUDE/ D+ \/ c5 ]4 e& ^3 v; E
739116 EMI SIMULATION At EMI simulation on SigXP an extra Sigwave form is launched.
* }' c/ R1 W9 g& _7 H0 p739225 ALLEGRO_EDITOR GRAPHICS Ability to lock the 'Hide Pallette' option+ f5 K! ?( G5 n; T- A. t/ |
739599 ALLEGRO_EDITOR DRC_CONSTR drc_errchk indic
+ j3 k8 M' b O- V4 w" _739628 ALLEGRO_EDITOR SYMBOL Opening a symbol file is crashing allegro.2 T5 F" }& k4 U0 k! X
739653 ALLEGRO_EDITOR SHAPE Shape created in 15.X .dra changes geometry when uprev'd to 16.X
# v8 @* T3 H% B& [: O739661 ALLEGRO_EDITOR OTHER Export netlist creates incorrect via_list syntax.
0 q: W6 t5 ]9 t0 j4 t( ^, v# N739872 ALLEGRO_EDITOR SKILL Crash while performing axlExtractToFile in 16.3& B3 W+ U9 b* v- x8 D& E
739934 SIG_INTEGRITY OTHER specctraquest crash on changing signal model
: J. n* }- p; Q. l0 q4 F/ R: m* V739937 MODEL_INTEGRIT PARSE zero valued estimated parasitics in ibis models
9 d) S# }3 P& r$ a! b k739942 ALLEGRO_EDITOR SHAPE zcopy xhatch shape creates oversize copy
8 m: |/ f7 M. J1 a" ]740133 ALLEGRO_EDITOR DRC_CONSTR Same net DRC Update from Analysis Modes runs forever.7 a" W. \8 a& Z _! U
740281 ALLEGRO_EDITOR OTHER Jumper components where were placed in PCB disappeared
" _1 m' s" N1 k: `. K6 K740309 SIP_LAYOUT DIE_EDITOR Moving a die pad in DIE EDITOR on G69A_U1 causes the die pads to rotate 90 degrees from the design.
$ m) g0 q$ f7 E' m4 i$ L) r q! |4 D740399 ALLEGRO_EDITOR COLOR Cannot automatically load custom color palette in 16.2
4 t7 d" W) U6 F/ U# f' C741210 ALLEGRO_EDITOR DATABASE Edit >Move; spin creates 'connect record not found' message$ A" a, H& \6 i0 d$ C+ N: m4 B
741307 ALLEGRO_EDITOR PADS_IN Shapes on some layers is not getting translated from PADS into Allegro6 B2 A+ A# J) R3 S4 F8 v$ |
741313 ALLEGRO_EDITOR DRC_CONSTR Add connect slow in 16.3% r- Y |' H0 S+ d
741778 ALLEGRO_EDITOR COLOR Color pallete in 16.3 is not expanding when maximize dialog
- a/ m, E! Q- ~' Y+ [741910 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd- m0 ?' T9 s/ t' ^
741939 ALLEGRO_EDITOR PADS_IN PADS to Allegro Translation fails or hangs.! O3 T: }; K1 o0 ]
741980 ALLEGRO_EDITOR PARTITION Import of parition does not import etch or vias.: o2 m( Q' h8 s. h. R" N
742676 ALLEGRO_EDITOR SKILL Tpoint cannot be moved by using skill.$ R% M" o1 N- K3 h! Q p
743161 ALLEGRO_EDITOR SCHEM_FTB Netrev crashing when importing netlist into board file.0 k8 n2 m9 k8 {: ?3 ?
743235 ALLEGRO_EDITOR PLACEMENT Allegro crashes when unmatching comp in placement replicate.
7 H+ d0 C* z6 E8 `5 d4 ^1 g5 K i, R743243 CONSTRAINT_MGR TECHFILE Closing CM destroys tcf values when they are set to locked using fObjectNOTReadOnly9 I" r9 o" D/ f9 b2 H+ Z
743301 SIP_LAYOUT DIE_EDITOR Edit die command creates two extra die pads
) S8 g1 z, R, M' X, H2 w743316 CONSTRAINT_MGR DATABASE With Allegro 16.3 Constraint manager takes to long to update, @* q& R* K2 W
743553 CONSTRAINT_MGR OTHER Net disappears if we cancel the line width edits in CM |
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发表于 2010-6-3 12:25
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