SystemVerilog for Verification

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SystemVerilog for Verification:
A Guide to Learning the Testbench Language Features
: @  D% U( i4 C+ _2 Y- ?) i1. VERIFICATION GUIDELINES 1
# s8 m5 H+ Q3 U; B- s6 L' y1.1 Introduction 1
/ v9 H9 @6 D. J0 x1.2 The Verification Process 2
1 l5 q$ A. j+ O3 z7 L' c1.3 The Verification Plan 4
1.4 The Verification Methodology Manual 4
( [) W" p2 I7 }! `1 R1.5 Basic Testbench Functionality 5
! S5 L% P: Z- t: i, d5 @1.6 Directed Testing 5
7 G" s* d! I+ v' X0 K0 S1.7 Methodology Basics 7
# e* V6 |& O& @& z1 C1.8 Constrained-Random Stimulus 8
1.9 What Should You Randomize? 10
1.10 Functional Coverage 13
/ g4 v; \6 Z0 S, d" {1.11 Testbench Components 15
6 y' s6 ]+ h1 D0 u# q. c- [1.12 Layered Testbench 16
1.13 Building a Layered Testbench 22
- Z# j0 y. Y3 Q2 ?* [% O" R% |1.14 Simulation Environment Phases 23
8 U0 x7 X2 ?8 \; P1 }" F/ }2 h1.15 Maximum Code Reuse 24
& A  t/ s+ ~* r) q7 E1.16 Testbench Performance 24
+ D' Y  f: L2 U1 @1.17 Conclusion 25
1 b0 x- M0 `. v2. DATA TYPES 27
2.1 Introduction 27
1 Y3 B. y5 v+ G$ o8 |4 l( `% F# W# R9 z2.2 Built-in Data Types 27
viii SystemVerilog for Verification
2.3 Fixed-Size Arrays 29
2 R1 h* \! Y4 `% W- a8 G2.4 Dynamic Arrays 34
2.5 Queues 36
2.6 Associative Arrays 37
2.7 Linked Lists 39
2.8 Array Methods 40
; Z+ z! T& o* f' G5 o. s3 u2.9 Choosing a Storage Type 42
, M  k& }+ V  p* }8 ^: M2.10 Creating New Types with typedef 45
7 y5 y# i6 o, `- S6 V1 b+ Z- r, ?2.11 Creating User-Defined Structures 46
2.12 Enumerated Types 47
" Q, r+ a+ V1 w  R* Y2.13 Constants 51
2.14 Strings 51
2.15 Expression Width 52
2 F; m' e: k! D' Z: `# f( `2.16 Net Types 53
2.17 Conclusion 53
- x; S6 r# e" `6 a8 a+ u* U3. PROCEDURAL STATEMENTS AND ROUTINES 55
3.1 Introduction 55
9 y. A8 u& x! O6 a( N: M3.2 Procedural Statements 55
3.3 Tasks, Functions, and Void Functions 56
6 c9 ~) L1 A2 h. `6 I3.4 Task and Function Overview 57
+ y$ P& S5 `4 t# C* s# v3 S3.5 Routine Arguments 57
3.6 Returning from a Routine 62
; S3 r4 G' O3 R3.7 Local Data Storage 62
3.8 Time Values 64
3.9 Conclusion 65
4. BASIC OOP 67
2 N7 T# }6 @" z* u/ c. ^1 Y5 L4.1 Introduction 67
" F9 l" G6 z$ c4 M0 n% @  A4.2 Think of Nouns, not Verbs 67
+ D/ E% X! N1 x9 S: R4.3 Your First Class 68
7 |8 {' q+ N3 ~" B# R9 a; K4.4 Where to Define a Class 69
4.5 OOP Terminology 69
4.6 Creating New Objects 70
" D; v/ C! \/ y( _$ X6 d1 x0 Q4.7 Object Deallocation 74
0 T0 c/ b. q% s5 ?- Y4.8 Using Objects 76
* K7 p1 b+ t7 o: j$ Q4.9 Static Variables vs. Global Variables 76
4.10 Class Routines 78
4.11 Defining Routines Outside of the Class 79
4.12 Scoping Rules 81
4.13 Using One Class Inside Another 85
5 T6 |% ]6 d" F7 y! a4 z9 {4.14 Understanding Dynamic Objects 87
  \8 r% g9 J9 Y) q4.15 Copying Objects 91
% H6 W8 Q$ d1 D6 |, g: W* H4.16 Public vs. Private 95
Contents ix
. t& A& p& K4 m! |5 u. A) Y  Y4.17 Straying Off Course 96
7 X; F5 s: B0 n; d' @- i# T4.18 Building a Testbench 96
4.19 Conclusion 97
; D' i7 f/ I0 _* }: E5. CONNECTING THE TESTBENCH AND DESIGN 99
! `6 H8 C! L. U& C4 S5.1 Introduction 99
5.2 Separating the Testbench and Design 99
/ m& h- S' E# j" R1 d9 ~5.3 The Interface Construct 102
0 y1 \( }; `; W, O9 C, Y5.4 Stimulus Timing 108
! S2 C" e: \" Q; o" {5.5 Interface Driving and Sampling 114
5.6 Connecting It All Together 121
5.7 Top-Level Scope 121
5.8 Program – Module Interactions 123
5.9 SystemVerilog Assertions 124
5.10 The Four-Port ATM Router 126
1 d" A, K' C& O; P5 q1 ^- x$ W5.11 Conclusion 134
0 {, N+ {5 D1 B0 ?% X) q6 ]6. RANDOMIZATION 135
6.1 Introduction 135
+ t0 l" e; v$ v+ R& z* _0 o6.2 What to Randomize 136
6.3 Randomization in SystemVerilog 138
- h! ?5 {9 u: x3 _2 Z! |3 n4 v6.4 Constraint Details 141
6.5 Solution Probabilities 149
6.6 Controlling Multiple Constraint Blocks 154
  F* v3 ~% m% k" v  F6.7 Valid Constraints 154
6.8 In-line Constraints 155
8 h& }: k0 j1 ]* M( i' Q6.9 The pre_randomize and post_randomize Functions 156
1 ^( n4 q2 `" U2 j6.10 Constraints Tips and Techniques 158
6.11 Common Randomization Problems 164
. O& i0 X  n2 B3 T, d9 i, P6.12 Iterative and Array Constraints 165
6.13 Atomic Stimulus Generation vs. Scenario Generation 172
6.14 Random Control 175
+ }7 Q1 m: S- G+ E% k% r6.15 Random Generators 177
6.16 Random Device Configuration 180
6.17 Conclusion 182
0 I2 v$ ]7 D& p+ m) `  Z: U7. THREADS AND INTERPROCESS COMMUNICATION 183
4 f  b9 G/ s% q0 D4 h7.1 Introduction 183
7.2 Working with Threads 184
7.3 Interprocess Communication 194
7.4 Events 195
7.5 Semaphores 199
7.6 Mailboxes 201
7.7 Building a Testbench with Threads and IPC 210
  ^) A2 @, H0 o) Dx SystemVerilog for Verification
7.8 Conclusion 214
$ b6 G2 ~  ]! N, q8. ADVANCED OOP AND GUIDELINES 215
8.1 Introduction 215
; w2 Q- J. C1 |1 v( o: A$ \8.2 Introduction to Inheritance 216
8.3 Factory Patterns 221
8.4 Type Casting and Virtual Methods 225
$ p" g- R3 {- R1 F4 k8.5 Composition, Inheritance, and Alternatives 228
; v( E" F0 E' u5 ?* y9 T8.6 Copying an Object 233
8.7 Callbacks 236
8.8 Conclusion 240
1 [/ {: z8 o) a' Y( L1 x9. FUNCTIONAL COVERAGE 241
% w* A; a$ N' }6 P. A$ q9.1 Introduction 241
! a$ s+ v- J' |$ S9.2 Coverage Types 243
9.3 Functional Coverage Strategies 246
+ D, c: j9 p% v6 Z& |9.4 Simple Functional Coverage Example 248
% [3 q8 ?7 c) `8 C# }9.5 Anatomy of a Cover Group 251
9 x* N: T: {, M' ^9.6 Triggering a Cover Group 253
9.7 Data Sampling 256
9.8 Cross Coverage 265
; V5 J! Q" A# k& C) Z$ U* y9.9 Coverage Options 272
- P% C5 N- H$ q% f8 }: M9.10 Parameterized Cover Groups 274
9.11 Analyzing Coverage Data 275
( W# z& ^& v" J0 k; l  H9.12 Measuring Coverage Statistics During Simulation 276
9.13 Conclusion 277
! i4 \% }8 U. z& o- x10. ADVANCED INTERFACES 279
8 Q$ i( ^# U, s8 |10.1 Introduction 279
10.2 Virtual Interfaces with the ATM Router 279
2 M# o4 X" M" C  w10.3 Connecting to Multiple Design Configurations 284
, e2 U! ]. U: ]& H10.4 Procedural Code in an Interface 290
10.5 Conclusion 294
  f" a5 y% }0 J) eReferences 295
Index 297

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