SystemVerilog for Verification

xuzwg

* I% \, E% ^* ?/ G2 ySystemVerilog for Verification:
( y: b- k9 B7 m4 j% ZA Guide to Learning the Testbench Language Features
1. VERIFICATION GUIDELINES 1
8 M" j2 k$ p, S3 x' k3 @* t8 S1.1 Introduction 1
$ K# b7 f8 _8 E" z4 q0 R1.2 The Verification Process 2
8 b. E" ^5 D9 M7 C+ _4 K7 ^/ x/ w1.3 The Verification Plan 4
% ^: v: z/ x% P7 B/ o+ Q" c1.4 The Verification Methodology Manual 4
% L* y/ i/ t! g  p* D. N' @  H! b+ _1.5 Basic Testbench Functionality 5
1.6 Directed Testing 5
4 Z6 p* i/ H, d3 a1.7 Methodology Basics 7
1.8 Constrained-Random Stimulus 8
1.9 What Should You Randomize? 10
) G3 `( m) f, `: P2 Z/ A6 T0 ?1.10 Functional Coverage 13
1.11 Testbench Components 15
1.12 Layered Testbench 16
1.13 Building a Layered Testbench 22
1.14 Simulation Environment Phases 23
- W# Z2 Z  Y1 z; y. \! h0 j4 [' S  T1.15 Maximum Code Reuse 24
1.16 Testbench Performance 24
: F! R6 C6 }. G5 ~1 n: B* T1.17 Conclusion 25
! Q$ l, c5 }1 b( |2. DATA TYPES 27
: v! G8 {) a* y2.1 Introduction 27
2.2 Built-in Data Types 27
viii SystemVerilog for Verification
; ?! \1 i3 t( \9 N+ A2.3 Fixed-Size Arrays 29
9 D  C) B* M) B6 g3 z2 _2.4 Dynamic Arrays 34
/ S# S- U. N8 C7 L: a6 n/ {3 _2.5 Queues 36
2.6 Associative Arrays 37
2.7 Linked Lists 39
2.8 Array Methods 40
1 F) Q; {# `! s8 Y$ q$ _" P& B2.9 Choosing a Storage Type 42
2.10 Creating New Types with typedef 45
- Z4 b9 i  m5 z5 N$ \  `2.11 Creating User-Defined Structures 46
& Z/ O, p9 y$ Q8 E( j5 R5 b2.12 Enumerated Types 47
) u& |* R0 ^5 l3 ^2.13 Constants 51
2.14 Strings 51
+ ?4 W! o2 q0 `9 A' K7 `2.15 Expression Width 52
2.16 Net Types 53
7 @! D! p) F8 o! E2.17 Conclusion 53
3. PROCEDURAL STATEMENTS AND ROUTINES 55
8 `* @: S; g2 _4 I3.1 Introduction 55
/ s5 ^! Y+ Z! b& _% K! L3.2 Procedural Statements 55
4 x0 Y, N" o$ o: F0 {2 s8 r3.3 Tasks, Functions, and Void Functions 56
7 U; u+ s" i/ w1 Q  E" l3.4 Task and Function Overview 57
3.5 Routine Arguments 57
3.6 Returning from a Routine 62
( a- k6 w, [" O' X3.7 Local Data Storage 62
3.8 Time Values 64
3.9 Conclusion 65
4. BASIC OOP 67
4.1 Introduction 67
4.2 Think of Nouns, not Verbs 67
- s9 P, |6 }' y7 o* e& J) z7 w1 N4.3 Your First Class 68
) b1 _" x  B  K0 J; ]9 Z9 m4.4 Where to Define a Class 69
  r0 k8 a. Y# h/ q$ }4.5 OOP Terminology 69
8 T* B6 Q9 L& G9 o; _) Y" q0 g' e4.6 Creating New Objects 70
4.7 Object Deallocation 74
4 E9 a" M+ F! c/ o4.8 Using Objects 76
4 w) D7 j) S' }* d) D, B4.9 Static Variables vs. Global Variables 76
4.10 Class Routines 78
4.11 Defining Routines Outside of the Class 79
4.12 Scoping Rules 81
4.13 Using One Class Inside Another 85
* G. p7 L" C4 w( h4.14 Understanding Dynamic Objects 87
3 }7 I- b9 S5 X+ C3 I4 Z, X/ g4.15 Copying Objects 91
4.16 Public vs. Private 95
Contents ix
8 L% r6 L3 f# w" p2 E4.17 Straying Off Course 96
4.18 Building a Testbench 96
4.19 Conclusion 97
5. CONNECTING THE TESTBENCH AND DESIGN 99
* B0 y1 b* n1 N. I5.1 Introduction 99
$ l, ~0 X3 t/ o( j6 ~7 i. U0 S5.2 Separating the Testbench and Design 99
5.3 The Interface Construct 102
% w8 p* H( N7 O% `/ c" Z( V$ ]5.4 Stimulus Timing 108
9 {- [% u2 D. {. w5.5 Interface Driving and Sampling 114
5.6 Connecting It All Together 121
/ c' d+ I9 T4 v5.7 Top-Level Scope 121
5.8 Program – Module Interactions 123
9 C! ?/ A4 s0 a) H: M+ W" S5.9 SystemVerilog Assertions 124
# T& {& e: f7 A- G. C* D5 E5.10 The Four-Port ATM Router 126
1 n4 {) N' s# b# m5.11 Conclusion 134
6. RANDOMIZATION 135
7 I9 R( r4 M- ^! s  M6 ?) ^6.1 Introduction 135
6.2 What to Randomize 136
6.3 Randomization in SystemVerilog 138
: M5 ~7 [% i2 b: V6.4 Constraint Details 141
* N8 ~. w& |- M' R3 K! W6.5 Solution Probabilities 149
' s' p" C, P: k8 r; j6.6 Controlling Multiple Constraint Blocks 154
6.7 Valid Constraints 154
( T: {+ V. c  R: Q6.8 In-line Constraints 155
6.9 The pre_randomize and post_randomize Functions 156
6 I) j8 x- }. L# q5 D% q0 d6.10 Constraints Tips and Techniques 158
" S5 T' W& G$ [1 N" `; B6 `; P6.11 Common Randomization Problems 164
! U. m+ B! q0 W6.12 Iterative and Array Constraints 165
6.13 Atomic Stimulus Generation vs. Scenario Generation 172
, V/ U' }- E1 Y8 e+ i8 G/ k7 t6.14 Random Control 175
# e0 b9 u! Y4 \% I/ h) x' v6.15 Random Generators 177
& L$ K& Z- m* V5 C% a+ U6.16 Random Device Configuration 180
6.17 Conclusion 182
7. THREADS AND INTERPROCESS COMMUNICATION 183
1 c8 Z6 T/ A$ T! M2 o$ K7.1 Introduction 183
7.2 Working with Threads 184
* ~. s+ W2 G2 i7.3 Interprocess Communication 194
: w7 n. I! L5 T7 \/ b7 w- C7.4 Events 195
5 X; \$ v% ^/ _; s" _7.5 Semaphores 199
7.6 Mailboxes 201
7 F  T  w+ r6 I  Y  {$ g% g( K3 s7.7 Building a Testbench with Threads and IPC 210
x SystemVerilog for Verification
- w+ L# s9 L  P, \. ?7.8 Conclusion 214
8. ADVANCED OOP AND GUIDELINES 215
8.1 Introduction 215
8.2 Introduction to Inheritance 216
8.3 Factory Patterns 221
  K: I" }$ S" q8 ~/ ]% W0 T8.4 Type Casting and Virtual Methods 225
8.5 Composition, Inheritance, and Alternatives 228
- i9 ]% E9 {2 e  F) r& h( v8.6 Copying an Object 233
: }+ h" }7 w* c4 [9 V4 {9 x/ R8.7 Callbacks 236
' ^: d9 X# |% g$ Z+ @, |' Q+ s' |8.8 Conclusion 240
5 I. _6 U4 p/ j' ]4 u3 ^9. FUNCTIONAL COVERAGE 241
9.1 Introduction 241
9.2 Coverage Types 243
9.3 Functional Coverage Strategies 246
9.4 Simple Functional Coverage Example 248
( C4 [5 @* X9 G  U  O7 l7 D$ F9.5 Anatomy of a Cover Group 251
2 B$ `2 r: S, m9.6 Triggering a Cover Group 253
, g3 u1 b% D/ X8 o% p/ g9.7 Data Sampling 256
, k% V2 x6 P1 O6 f" d' Q6 ?  |9.8 Cross Coverage 265
9.9 Coverage Options 272
9.10 Parameterized Cover Groups 274
9.11 Analyzing Coverage Data 275
9.12 Measuring Coverage Statistics During Simulation 276
9.13 Conclusion 277
" q; l/ v. v" k& f( X9 ]10. ADVANCED INTERFACES 279
10.1 Introduction 279
' Q$ V! B+ ?& ~# o10.2 Virtual Interfaces with the ATM Router 279
10.3 Connecting to Multiple Design Configurations 284
10.4 Procedural Code in an Interface 290
: m4 H2 }8 `- N9 f; s" p! H10.5 Conclusion 294
* V& W6 w  E* d/ z- VReferences 295
( O& w- B* v: {) J5 ?) rIndex 297
$ N$ M0 X1 B1 s5 x0 T

xuzwg