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换了nandflash后和加焊DDR后有两种状态,但是板子都没有启动成功,串口有打印。! ]8 n3 N/ u( O( h
以下是状态1的log:/ [" h5 B; D2 r3 S5 z. B
SoC preloader 1.0.0.r1422.lzma (Wed Nov 13 14:32:57 CST 2013)
3 Z. r, ^+ }4 e# `" H! u0 bII: Stack @ 0x9fc1fd18 (parameter 736B)
+ L- }* ~' a5 E4 _& q' {8 S& OII: Console... OK. o0 P0 n- |+ k6 I, s8 q' v! {
Setting DTR
/ n o% k# a: l3 \II: DRAM is set by software calibration... PASSED6 Z+ I4 _) b; c* b
& w2 m7 Z8 [7 iDDRKODL(0xb800021c):0x00000410
) B! `: O, o2 XMCR (0xb8001000):0x22041de0, 0x21220000, 0x54433830, 0x0404030f0 e$ W+ @# N$ U3 U# f! x5 ~
DTR2(0xb8001010):0x0630d000
2 [1 F; y# o3 wPHY Registers(0xb8001500):
. T* t! @$ J7 ]6 N/ [3 H. I0xb8001500:0x80000010, 0x0000007f, 0xa1a00000, 0xfdffffff* Z- @" Y& Z; U+ V2 F
0xb8001510:0x00140a00, 0x00180c00, 0x00140a00, 0x00180c00
! F* z: w/ F g: E0xb8001520:0x001a0d00, 0x00140a00, 0x00160b00, 0x00120900% s6 R2 s0 A3 o$ R1 e2 N
0xb8001530:0x001c0e00, 0x001e0f00, 0x001c0e00, 0x001e0f00" r3 o: o1 `8 Y% S3 m( S, r
0xb8001540:0x001e0f00, 0x001a0d00, 0x001c0e00, 0x001a0d009 `7 x) S! F/ I( t. ?, N. L
0xb8001550:0x00100800, 0x00140a00, 0x00100800, 0x00140a005 m( e& x$ m; m: I
0xb8001560:0x00160b00, 0x00120900, 0x00140a00, 0x00100800/ s9 F: ~1 D; [* R2 z5 w, N
0xb8001570:0x001a0d00, 0x001a0d00, 0x00180c00, 0x001c0e00# _! H; I- g+ [
0xb8001580:0x001c0e00, 0x00180c00, 0x001a0d00, 0x00180c00# L j2 R1 Q6 v; L2 C& s6 X' k5 ], R& P
0xb8001590:0x00000000, 0x5110dbd9, 0xa9a95656, 0x5352b5b5
: I, D p D5 i+ E8 X7 Z0xb80015a0:0x4145dcdc, 0x00000000, 0x00000000, 0x00000000
) m/ [5 U- }. U0 X0 E. |9 @II: PLL is set by SW... OK& `8 C3 y D# l6 A
II: Flash... OK- _, w5 m# T4 K% i
II: Stack @ 0x801ffff8; B" s6 A0 W9 d7 V5 g8 {
II: Starting U-Boot...
9 _1 y7 C* X5 ]II: Inflating U-Boot (0x80000040 -> 0x87c00000)...
' j# @5 Q( B% I- E/ UEE: decompress failed: 1
0 V0 s0 O1 I1 L* H以下是状态2板了log:
8 ]8 ~% Y0 C" k0 P/ l2 b/ jSoC preloader 1.0.0.r1422.lzma (Wed Nov 13 14:32:57 CST 2013)
% |% \$ e& h4 oII: Stack @ 0x9fc1fd18 (parameter 736B)* E$ K0 P5 ?# x/ ~3 t# N7 \
II: Console... OK
/ v4 F/ n; l/ Z6 nSetting DTR
$ N' s' V$ U$ {( l8 S4 ^II: DRAM is set by software calibration... PASSED
% a* V3 F- a y6 \' t
2 y9 w! a: e% {. U4 o& D# kDDRKODL(0xb800021c):0x00000410: ~) h" _: g$ ?2 f
MCR (0xb8001000):0x22041de0, 0x21220000, 0x54433830, 0x0404030f+ N( z q5 C" p& k5 I
DTR2(0xb8001010):0x0630d000
" @! e+ l* H: X+ q1 VPHY Registers(0xb8001500):5 g( {8 G1 x& i3 C
0xb8001500:0x80000010, 0x0000007f, 0xa1a00000, 0xffffffff
9 ^! y* Y0 b7 r' I* @; a# H0xb8001510:0x00120900, 0x00140a00, 0x00120900, 0x00160b00 J T9 ]" a& [5 j" D
0xb8001520:0x00140a00, 0x00120900, 0x00140a00, 0x00100800
( W2 M1 y: Z. k; b0xb8001530:0x00180c00, 0x001a0d00, 0x00180c00, 0x001a0d00
' t9 a1 Q- t0 j" |5 u! o0xb8001540:0x001a0d00, 0x00180c00, 0x001a0d00, 0x00180c00
1 `, B) F' K% K; I z0xb8001550:0x00120900, 0x00160b00, 0x00120900, 0x00140a00% u3 U6 H$ M4 N* n5 N, b$ S# u
0xb8001560:0x00140a00, 0x00140a00, 0x00120900, 0x00100800
7 g: J8 J/ G; S6 O1 b. A0xb8001570:0x001c0e00, 0x001c0e00, 0x00180c00, 0x001c0e00
3 S: ^& E: n# \- F0xb8001580:0x001a0d00, 0x00180c00, 0x001a0d00, 0x00180c00
4 }4 e" }& ^; b# x9 x/ \& C0xb8001590:0x00000000, 0x5adad2d2, 0x24207574, 0x5a5adada
- A, {* B7 c4 l. G. ^: x0xb80015a0:0x8d0da7a5, 0x00000000, 0x00000000, 0x00000000
0 _6 D: |* i; C5 ~/ lII: PLL is set by SW... OK
! i2 i: m! u r; n) N4 ` ^/ W' X4 FII: Flash... OK$ y: j: p2 e1 e) }/ M# f
II: Stack @ 0x801ffff8
7 `' [( z' k( Z& |6 c% M! p l7 KII: Starting U-Boot...8 B$ C- d7 V$ }+ J3 W8 f
II: Inflating U-Boot (0x80000040 -> 0x87c00000)... OK6 W+ l. A* k' ]" B- E: W. I5 I% u
II: Starting U-Boot...
* z4 m. {+ O6 |, q. _6 p! K1 M2 o( V0 J5 S0 B/ E
0 t" E! w6 `* g+ d& L T( gU-Boot 2011.12.NA (Nov 13 2013 - 14:33:03): k' V/ H. w x
& C8 G9 p' B. U$ l: MBoard: LUNA
: o* Q* U1 V( L0 s2 s: W6 n; pCPU: RLX5281 600.00 MHz, DSP: RLX5181 500.00 MHz, , DDR3 300MHz, LX:200.00 MHz 2 A! h* g; e. j, ~ D4 P, c' p$ F
DRAM: 128 MB
# J+ o K. o+ H0 ~3 `enter nand_init0 m$ B4 D3 c. A$ \/ O1 _
board_nand_init()
% q6 [* R4 S3 Y+ W# h6 d# kparameters at 0x00001212
9 ]1 l, P( b/ j2 jparameters.read at 0x9fc00550
+ e5 j0 r7 z$ V$ z) Bparameters.write at 0x9fc03308
7 A9 f2 _1 P N6 b6 {parameters.bbt at 0x9fc1feac
5 k" p4 F) n% c9 buboot- read nand flash info from SRAM" ^1 E0 m) z U# h- ]* ^# e7 w# O
flash_info list
+ ~2 b9 [7 \5 `8 _0 Bflash_info.num_block : 1024
6 \; a# T- P) e T9 j9 Y4 o% Aflash_info.num_page_per_block : 64# y9 Q5 B u) Q, p* K" y
flash_info.page_per_chunk : 1
, ^ T1 |2 R/ _( v* K, ^1 jflash_info.bbi_dma_offset : 2000/ S0 s7 v- K' I( @5 c, h2 l
flash_info.bbi_raw_offset : 20484 D- F5 H6 Z7 y
flash_info.bbi_swap_offset : 23/ A' R; i( c$ z( \; {8 L! G1 U
flash_info.page_size : 2048, v1 j0 d' g/ y- G5 ]) m& S4 P/ O
chunk size : 2048) h6 r! k5 V( P( U( F: b
flash_info.addr_cycles : 46 d# ]& U! b1 z% p9 G: j
pblr_start_block : 1; c, A/ ?2 x: ]% J5 j: N0 p9 g& ]0 k
num_pblr_block : 3; z( _/ T2 S) a# e9 y. q
parameters.curr_ver is a
2 P8 l X9 |% L7 }8 |parameters.plr_num_chunk is 29! @3 k0 n1 |& B+ B" u" B
parameters.blr_num_chunk is 45
k- g; T7 Y6 D! Rparameters.end_pblr_block is 4/ n8 Q" r0 {" W: _* ^5 s2 s
rtk_nand_read_id id_chain is 9580f192 P* k* ]* y" l2 D$ [6 ^8 i% R
nand: Manufacture ID=0x92, Chip ID=0xf1, 3thID=0x80, 4thID=0x95, 5thID=0x40, 6thID=0xc0
6 B' x4 u2 M7 j, v3 }this->pagemask is 65535
! I3 {1 n) e+ N7 K' o/ othis->chip_shift is 279 U( K( n& W. r7 m
parameters.bbt_valid is 13 [- T# x7 ~" ^, X
create_logical_skip_bbt
~5 |8 ^2 Y7 K/ u$ [4 Y' klast skip_block 1024! V5 I1 R5 T9 [
nand.c nand_init_chip mtd size is 877bfeac. {. j8 z) _3 [
128 MiB
) U' }8 u2 Q( ?: C4 sLoading 131072B env. variables from offset 0xc00008 Y8 @. m# ]4 S) A1 U) R- Y) ], B
Unknown command 'sf' - try 'help'
; N1 j* ^/ q: `Net: LUNA GMAC
* X% ~) f' m! s$ q# @* z; N7 oWarning: eth device name has a space!
6 g" U7 w6 [+ l( f: {: D* G9 Y0 l! Z' }1 S+ P0 y* L) X8 p
Hit space key to stop autoboot: 0 7 Z' I4 m( M( C
0 |- o$ z: {$ f- f8 X$ T
$ o% t$ z. _$ `ACTIVE IMAGE 0 (tryactive=2 sw_commit=0)
9 G' B* A1 M+ J' C$ Y& U( w$ O7 a
2 W1 T9 H8 a, M- c+ v# o0 O( v; v9 zreset pcie0
, T/ B- L$ o4 F9 T( @: w, y5 |# yreset pcie1
2 U D8 Z* K& X3 G( k4 W4 V* k0 l8 ~4 _" r( V
NAND read: device 0 offset 0x100000, size 0x380000
' a5 z# G f6 A; |0 z 3670016 bytes read: OK
+ i" ^( u8 O% b3 O* G/ k% ^## Booting kernel from Legacy Image at 82000000 ...
" Q' N j( I) p W& _0 f3 l Image Name: Linux-2.6.303 [! L1 @$ w' t* J M* k1 A
Created: 2013-11-14 2:56:37 UTC
0 K& e8 w% J3 C& o. _ Image Type: MIPS Linux Kernel Image (lzma compressed), s4 W9 f5 X5 `5 m r. d
Data Size: 1791872 Bytes = 1.7 MB
X! h% c+ i( ?4 t' [$ { Load Address: 80000000
3 y3 @, G" D) t1 t k Entry Point: 80000000
/ u" z; I, F6 c6 y Verifying Checksum ... Bad Data CRC* g0 t( z! E \( G2 O. b9 H
ERROR: can't get kernel image!; ~$ V7 }1 M8 Y' ]3 R f% F
5VT-2510#
1 {' R% v8 W/ B- g( [! V0 k请问大家这是什么问题呢? |
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