这个层次原理图为啥总报错呢？

winz

尝试画个层次原理图，很简单，就几个电阻一连，可是画完了DRC的时候总是报错：
+ ?; G! [0 j9 C7 QChecking Misleading Tap connection
1 ?4 y9 ^+ n0 ^ERROR [DRC0039]   Tap may not be connected with the bus Check Entire net. DD1:  SCHEMATIC1, top  (3.55, 2.30)
8 ~/ E, X1 W3 a' |/ M0 eERROR [DRC0039]   Tap may not be connected with the bus Check Entire net. DD2:  SCHEMATIC1, top  (3.55, 2.30)
ERROR [DRC0039]   Tap may not be connected with the bus Check Entire net. DD3:  SCHEMATIC1, top  (3.55, 2.30)
$ |# e3 j" L5 ^( [8 NERROR [DRC0039]   Tap may not be connected with the bus Check Entire net. DD4:  SCHEMATIC1, top  (3.55, 2.30)
3 `! g2 \! J1 L, Ehierarchical pin name D[1..4],
bus name DD[1..4],
net alias 分别为DD1，DD2，DD3，DD4。
问题出在哪呢？如果把根图上的bus name 去掉，就又报警了，
Check Bus width mismatch
8 L8 Y  ?: a" G6 X) I  I$ cN06946 has not connected with proper width
WARNING [DRC0030]   Bus width is not matching with the port Width block1,DD[1..4]:  SCHEMATIC1, top  (2.45, 2.30)
N06946 has not connected with proper width
WARNING [DRC0030]   Bus width is not matching with the port Width block2,DD[1..4]:  SCHEMATIC1, top  (3.55, 2.30)
% E# w' v6 I1 }3 v