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SDR新书:Baseband Analog Circuits for Software Defined Radio
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3 x1 _* N% K8 r6 QAuthor:
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5 b8 `1 D5 g. F7 s* _VITO GIANNINI
: F& M% q- v- n8 Q9 l; pJAN CRANINCKX
+ Y# L+ L2 k; i+ U+ mANDREA BASCHIROTTO 8 @& g9 ?- I( t8 b5 u$ o$ g1 h% A
IMEC, Wireless Research, Leuven, Belgium ! S7 r) @. A# H2 W+ I1 s& U7 v1 I
IMEC, Wireless Research, Leuven, Belgium : `1 A0 s4 s7 r/ {# p
University of Salento, Italy
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Contents 0 D8 R/ k) K% a' M
Dedication v % l: X% z& V2 N- k
Preface xi % X% P- e2 O3 I. z4 S: s
Acknowledgments xv 4 A4 O4 c* {! C" U0 L8 v5 M
1. 4G MOBILE TERMINALS 1
% K% _/ i0 H) z9 d( b* \1.1 A Wireless-Centric World 1
) r2 {( f6 B5 J+ l' x% |1.2 The Driving Forces Towards 4G Systems 3 ) e c! F( Z) G/ N7 B6 l
1.3 Basic Architecture For a 4G Terminal 6
+ b* j) e7 c# X G7 z5 ]; x1.4 The Role of Analog Circuits 8
( x" |: `! C4 |7 ?4 _4 w/ e* [; P1.5 Energy-Scalable Radio Front End 9
6 o+ X* w9 v; o5 o& K+ n1.6 Towards Cognitive Radios 11
" q8 f! c( G/ Z% p2. SOFTWARE DEFINED RADIO FRONT ENDS 13 8 X1 G$ k4 Q' z1 H
2.1 The Software Radio Architecture 13
! F) P0 ~3 I5 }- N& i% k2.2 Candidate Architectures for SDR Front Ends 16 + ~6 O j+ l# A4 k6 \1 o$ A* I. @
2.2.1 Heterodyne and digital-IF receivers 17
y+ g& C" h- f1 I2.2.2 Zero-IF receivers 19
, @. P) d8 ]# h- n2.2.3 Digital low-IF receivers 22
. |; R, t, G0 U* Z( v k! |' [! r2.2.4 Bandpass sampling receivers 24
3 e" ^7 J5 U- l1 S4 d2.2.5 Direct RF sampling receivers 26 / G: P% j: Z& s
2.3 SDR Front End Implementation 27
* z2 W0 J0 u, Y5 e2.3.1 LNA and input matching 29 2 s, g* ^# Z3 h3 c/ U0 Q. W
2.3.2 Frequency synthesizer 30 + B5 F% W, j6 M# s2 \$ h# }
2.3.3 Baseband signal processing 31 4 ~$ l5 \+ s% n! f" |* a
2.3.4 Measurements results 31 / b$ G- r* i! o) R& C
2.4 Digital Calibration of Analog Imperfections 33 $ A: J5 l0 L0 a( Q4 I6 s7 Q
2.4.1 Quadrature imbalance 34
1 R9 | k" a* a5 ?2.4.2 DC offset 36
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( y) Y7 u" _ ? XContents
5 Y |) y/ h9 ~3 }2.4.3 Impact of LPF spectral behavior 36
, B6 F' i2 f* I E- y6 j2.5 Conclusions 37
|* G( |' ?# [0 U: f1 U3. LINK BUDGET ANALYSIS IN THE SDR ANALOG
+ l3 Y" V( C- wBASEBAND SECTION 39 8 P$ O7 I$ u+ m7 m
3.1 Analog Baseband Signal Processing 39 5 }# V9 U' N" ?9 h3 @
3.2 Baseband Trade-Offs for Analog to Digital Conversion 40 / \; j( D) ?1 ]! z C: l' X" h
3.2.1 Number of poles for the LPF 41 % z) T& E: T3 w& a
3.2.2 ADC dynamic range 42
* ]1 m6 ^6 s5 ^- g5 k3.2.3 Baseband power consumption estimation 47
* z {# X% i! v6 T0 ^3.3 Multistandard Analog Baseband Specs 48
% E# a" V; V% E4 c7 \, {# K3.4 Multimode Low-Pass Filter 49
6 y2 e! _+ a6 V, b d3.4.1 Filter selectivity 50
, w3 @4 [# A& `- g0 |3.4.2 Filter noise and linearity 54 ! Z7 N- n+ ?, u2 ~& N& f
3.4.3 Filter flexibility planning 56 % z7 C8 z5 k3 T
3.4.4 Cascade of biquadratic sections 59 2 F* c% E, j2 `0 f/ Z$ b$ N
3.5 Automatic Gain Control 62 1 f- y; a/ |) @
3.6 Conclusions 65
/ v0 _0 Q6 k* T d( T9 _ P4. FLEXIBLE ANALOG BUILDING BLOCKS 67 2 R6 H" O; `, c& E3 q
4.1 Challenges in Analog Design for Flexibility 67 / R; H' k; q" t9 G
4.2 A Modular Design Approach 68 7 b# V6 W' n4 D) e1 f) L
4.3 Flexible Operational Amplifiers 70
1 d2 B, m8 s8 t% Y$ x* H: [4.3.1 Variable current sources 70
5 n [' M1 U% o* f4.3.2 Arrays of operational amplifiers 71 6 F$ h# {& ?, b j% s
4.4 A Digital-Controlled Current Follower 75
) |4 e0 X4 f/ j: q o* }4.5 Flexible Passive Components 75
5 P& F+ s( \" E6 y9 I# N; r5 N4.6 Flexible Transconductors 77 / ~4 \5 ~8 k* g
4.7 Flexible Biquadratic Sections 78
" U4 U. _" X) f1 [" r* x- C4.7.1 The Active-Gm-RC biquad 79 0 f6 [( I& G! ~2 n: D
4.8 Conclusions 91
' z$ G$ M. V _( F5. IMPLEMENTATIONS OF FLEXIBLE FILTERS FOR SDR
6 a0 l8 j2 U" xFRONT END 93
% k4 [. F( i H+ C! {- Z$ _6 Z6 L5.1 State of the Art for Flexible CT Filters 93
N4 `7 J) K5 q- {1 `5.2 A Reconfigurable UMTS/WLAN Active-Gm-RC LPF 94 " g. M; _1 E7 m+ K9 O
5.2.1 Filter architecture 96
2 a* F" ]% z2 V5.2.2 Automatic RC calibration scheme 97 # i% I/ M D% p* A5 H, X& l
5.2.3 Measurements results 102
. B8 h1 X' I3 b$ }6 P: \Contents
7 m. |8 k4 d- S( Fix
+ p7 U9 j Z* I0 j0 U) B: U5.3 LPF and VGA for SDR Front End 105 0 P. S) p/ v, S! }
5.3.1 LPF and VGA architectures 107 ) v5 G+ s2 z, c$ s( n
5.3.2 Prototype measurements 111
3 }5 k: r! Y+ { h2 U; m' s5.4 Conclusions 118
4 F) @- {; R1 W# a1 AAcronyms 119
! @( x1 a$ P/ s/ mList of Figures 123
. W9 z: Q" u4 t- RList of Tables 129 9 E. r0 p: I8 N5 v) \
References 131
, t. b) L) r( c vIndex 139! V9 ^! T( K7 T" a" K) n6 `7 p
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