对这段文字描述感觉有些困惑

mengzhuhao

对这段文字描述感觉有些困惑
: V- B, I) K1 O/ |; L
& c% `0 V  H! ?+ B; }
5 g7 A5 S4 o  l& c8.0 Actual "full_case" design problem
The 2-to-4 decoder with enable in Example 12, uses a case statement that is coded without using
any synthesis directives. The resultant design was a decoder built from 3-input and gates and
& l9 j$ R# L. g1 w! {/ r! iinverters. No latch is inferred because all outputs are given a default assignment before the case
/ X2 [# g: x! ?/ U: ystatement. For this example, the pre-synthesis and post-synthesis designs and simulations
matched. The 2-to-4 decoder with enable in Example 13, uses a case statement with the
# [9 c' R7 s: a"full_case" synthesis directive. Because of this synthesis directive, the enable input (en) was
optimized away during synthesis and left as a dangling input. The pre-synthesis simulation
1 F" N& p( M: ~9 L0 m' \results of modules code4a and code4b matched the post-synthesis simulation results of module
" D6 I5 Z* _5 M3 E9 [. A& Fcode4a, but did not match the post-synthesis simulation results of module code4b [2].
// no full_case
// Decoder built from four 3-input and gates
' H7 A0 [4 E; ^1 w// and two inverters
module code4a (y, a, en);
output [3:0] y;
input [1:0] a;
$ h) q' L! ?5 S; Z  yinput en;
reg [3:0] y;
always @(a or en) begin
y = 4'h0;
7 T5 }! s+ n0 ^  l" I% D9 Y  Scase ({en,a})
3'b1_00: y[a] = 1'b1;
3'b1_01: y[a] = 1'b1;
3'b1_10: y[a] = 1'b1;
3'b1_11: y[a] = 1'b1;
endcase
end
endmodule
" \4 y- o* X5 B6 k3 p+ q% PExample 12 - Decoder example with no "full_case" directive
Statistics for case statements in always block at line 9 in file
& B: o% [8 h4 F& w7 v* v'.../code4a.v'
===============================================
3 G1 x- j4 b# ]| Line | full/ parallel |
2 N0 X( L0 C% I/ N- o9 P===============================================
| 12 | no/auto |
" ~. X/ g% x/ @& ~5 M2 c( \7 _/ n===============================================
- A, L# @( E9 o0 nFigure 19 - Case statement report for Example 12
  _, S& o. y8 a; x, \: `

// full_case example
// Decoder built from four 2-input nor gates
/ _$ f& y$ m/ ]9 n! o// and two inverters
4 U# Z% o9 W3 q9 j. k3 u9 k// The enable input is dangling (has been optimized away)
6 y& B4 n' i' f4 S# jmodule code4b (y, a, en);
output [3:0] y;
input [1:0] a;
input en;
1 n- X/ `9 Q# ~: k, z" Kreg [3:0] y;
, c) k1 \; ^) l, B& ^2 Palways @(a or en) begin
y = 4'h0;
6 k5 ]. Z7 ?* n3 fcase ({en,a}) // synopsys full_case
3'b1_00: y[a] = 1'b1;
3'b1_01: y[a] = 1'b1;
  U4 R) j) e2 ]6 R5 U  }3'b1_10: y[a] = 1'b1;
3'b1_11: y[a] = 1'b1;
& p& e$ l$ ~6 eendcase
4 v/ X4 [7 e9 Lend
endmodule
+ L& u8 ~4 Y; zExample 13 - Decoder example with "full_case" directive
Warning: You are using the full_case directive with a case statement in which
not all cases are covered
Statistics for case statements in always block at line 10 in file
'.../code4b.v'
===============================================
| Line | full/ parallel |
6 k. q0 @( Y& N- E* t5 n7 N  p===============================================
7 R4 b4 f1 X. I2 k2 q% r6 R* V. f| 13 | user/auto |
===============================================
, X3 I9 w; ]; Q8 `4 `1 EFigure 20 - Case statement report for Example 13
4 V; y5 W- [2 P# o2 }
% P: V7 S; i6 `+ Y) `* i谁给解释一下原因呢?
/ D+ Z; I9 k% d3 T8 g为啥会有差异?