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DATE: 08-22-2014 HOTFIX VERSION: 034
6 M2 c/ u% \4 L8 u; Z6 U4 q===================================================================================================================================4 B4 s- ]9 a3 }2 S( D1 s! A" X
CCRID PRODUCT PRODUCTLEVEL2 TITLE
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& K% B0 w* Z: M) l932528 CONCEPT_HDL OTHER Ability to handle reusemodule in soft reuse blocks.
( B) a% Y# ^) H; r4 {- E1137838 FSP GUI Ability to add notes to the canvas
2 m8 ]2 q% A7 N. B& j# }& M' H0 r) p1274382 ALLEGRO_EDITOR OTHER Retaining rats at the end of the clines or vias
' S0 b2 j3 z+ v" G" @' x& Z% g1283575 FSP DE-HDL_SCHEMATIC Force Schegen to use symbols from released library
+ o1 v" ]: b) m+ O0 i$ A9 M4 h1296331 CONCEPT_HDL COMP_BROWSER CSV export no longer works properly from Component Browser
, c( v% E4 |% [" S9 t1297855 F2B DESIGNSYNC ds -automode error
* z$ A' X7 }9 U; h1298028 CONCEPT_HDL CREFER CreferHDL crashes
+ E& H5 z1 [$ J+ {1299607 SIG_INTEGRITY OTHER AutoModel should generate ESpice models for illegal values& ~* B' `0 f2 j9 |' `
1299609 CONCEPT_HDL OTHER AutoModel should make an ESpice model for a 3 pin Capacitor
0 S9 v1 F( M- o/ ` J- U1302013 ALLEGRO_EDITOR EDIT_ETCH AiBT Crashes Allegro for nets having T points* B4 h, C) M. j( }7 d
1302209 SPIF OTHER Can't Export to Router and create a Specctra file.
5 ?/ S# ?5 ]" P) K; E1302242 F2B PACKAGERXL Packaging a hierarchical project does not create a full pstdmodeldat file7 p: y; q" c' {3 _' X
1302285 SCM CONN_SERVER DSCS-120: Failed to open file <filename.xcon> in write mode$ [% X8 H( L- N2 M6 m; o6 |
1302310 ALLEGRO_EDITOR INTERFACES Need way to have user defined license packages win over Cadence products.
5 w* R/ r# ^! J" I8 O, P2 W5 I- A. p1302638 F2B PACKAGERXL Function swaps are not backannotated into the schematic# P5 G9 T* d# @9 O9 G
1303170 SIP_LAYOUT DIE_STACK_EDITOR Using Die Properties to move a die to the bottom side causes some entities to disacociate from the part( E: h3 k5 c( K: O2 o
1303214 CONCEPT_HDL CORE DEHDL crashes
! b2 w* `" q. ], l, j9 g; A; U1303219 ALLEGRO_EDITOR COLOR The user preference variable color_dlg_auto_apply changes the colors in the Display category
1 e" I2 c9 [7 U' P1303685 CONCEPT_HDL CORE DEHDL crashes when I save page 3+ ]$ w- @. G0 `& U
1303897 CONCEPT_HDL CORE Tool crashes intermittently when editing top-level schematic
3 _) w* I: x5 \7 S1304656 APD PLATING_BAR Add Plating Bar command convert the Clines having Arcs to 45 Degree segments+ f% z4 r- L# Z% E- N
1306467 CONCEPT_HDL CORE Concepthdl crashes during model assignmnt" z: l9 s2 F9 _1 p2 r) p
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功能上的更新了 color_dlg_auto_apply 应用;勾选了此项后;设置颜色时不需要点击应用按钮了;显示很直观哦& P! W! m. q7 w4 J) n, Q
大家来试试吧( {# z! E3 T0 |) }3 i( D$ W% R
不足之处就是出钻孔文件导入cam350时单位精度还是有问题的;特别是勾选了CAM350后比例更加有问题。% @2 Q& O; R) J3 g4 A5 [
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