这段文字如何理解呢？为何会进入亚稳态？

mengzhuhao

这段文字如何理解呢？为何会进入亚稳态？

If the asynchronous reset is released at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.

mengzhuhao

The biggest problem with asynchronous resets is that they are asynchronous, both at the
assertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the
, b$ G/ ]2 R8 r) j9 ~' iissue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the
* k. F8 u: G; {$ y% e. S0 uoutput of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.
7 _# H  Q3 ~! }7 GAnother problem that an asynchronous reset can have, depending on its source, is spurious resets
due to noise or glitches on the board or system reset. See section 8.0 for a possible solution to
8 }# ^, r. I* j  ereset glitches. If this is a real problem in a system, then one might think that using synchronous
6 h) ?  N  f9 J9 H" |1 p( oresets is the solution. A different but similar problem exists for synchronous resets if these
9 B! w$ @5 H  N# X7 k6 |spurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is
. w; m& Q+ c, C0 z. G8 ztrue of any data input that violates setup requirements).