|
|
本帖最后由 stupid 于 2013-4-30 23:17 编辑 ( N5 n/ b) k# o/ B) X. M
; W) I( `* v; h! r# E4 g' ?, S某一天，一个叫马克的人发起了帖子，采用了滚动刷屏的方法，4个帖子，一个内容：招人
( w6 W, Y, g( I, H E8 \$ g
9 P( r1 d: W+ ]% V. m+ n首帖Date: Mon, 7 Jan 2013 17:36:56 +0000$ |1 ^; U# d" ^/ D" o1 z0 `
2贴 Date: Fri, 15 Feb 2013 00:22:29 +0000+ ]% l9 h8 d, v9 o
3贴 Date: Thu, 14 Mar 2013 04:49:58 +0000: K" _& s0 l7 y* N5 N! L3 N/ k
4贴Date: Thu, 25 Apr 2013 18:37:34 +0000
6 z+ d# L0 l- k$ p$ ?3 A: Y4 L6 o: n9 i
My Team is looking for a Senior Staff Engineer(Backplane Architect)/Principle ' m( I) n9 f8 ~( U
Engineer;+ j! {8 S8 a( ~8 o) x% `4 Q7 m. |
Responsibilities/Description;: l. H: V o3 Z% a
Responsible for providing the backplane architecture and 10G+ High Speed SI
( d8 I6 E- q& n2 M6 z* C: `6 msolutions for Next Generation telecommunications equipment in the router,
M+ J7 I' F8 X$ [6 f4 S% `0 [8 Lswitch and transmission product lines to meet system design requirements.! v% M/ a5 p4 Z6 E* i# R, t! F' S: \
Experience in co-designing of ASIC, Package, PCB and System interconnects
3 b, Z; ~% r6 v- m6 }; k, K4 E6 kdesired. including:9 y1 Y) M5 S' S8 p$ j* `4 o
6 J0 T; \" M% p e# T6 D- Design and analysis of multi-gigabit serial links for Backplane and
1 R4 c4 f8 W. Q chip-to-chip interfaces meeting CEI, XFI, XLAUI, SFI, 10Gbase-KR, PCIe, and$ C% O1 P! e- |7 n
other standards.
d7 d* r9 M! B g- Familiar with ASIC, Hardware, interconnect teams to evaluate design& U" [) S( `* o- T0 ^9 M' S7 M
tradeoffs and optimize design performance / risk / cost /manufacturability.
5 D5 u, z5 }) p/ t' v6 Y- To evaluate package designs, characterization of SerDes, and design
2 F2 M- W( V% I" B3 _7 p1 ? experiments to do the same.
: `. h- T/ F f6 P: C) n8 j- v- Modeling of electromagnetic 3-D structures.
/ w; k* z1 ~, t9 U8 V/ H( h# h- Modeling and analyzing power delivery networks (PDN).7 y- u5 |6 h) m; }0 N
- Familiar with memory technologies such as DDR2/DDR3 is preferred.
" c" T; {1 F6 Z" l7 K- C0 F) T k+ D
Qualifications/Requirements:0 X5 r0 u8 m% s2 f4 L, c
2 V& g2 H0 g: M2 u4 A
- Performing physical measurements to collect data for design' t& ?% a/ C6 V1 n
validation and simulation correlations.
8 w* e( \# h/ b1 j* x5 ~1 \ v( q4 H- Knowledgeable in using most major SI/PI tools: HFSS, CST, HSPICE,
8 E/ J' e9 C9 O/ X: w+ O6 k Sigrity Tools, StatEye, ADS, Matlab, Cadence Allegro and APD, HSPICE, and) [1 L8 }4 d" j) ~
other tools.( B! @. p/ B% J5 x; }5 d; E
- Experience in correlating simulation results with lab measurements# l& P) \* t, l/ h. p9 M) y7 j
using oscilloscopes, TDRs, VNAs, BertScope is a plus. Must be self
3 A7 E8 L6 r2 Z$ d3 P% | motivated with strong communication and teamwork skills.1 ?7 w L/ M6 s" B0 @- m {
- The working experience in Core router or Edge router similar product0 Z6 P4 @7 c4 e8 B/ _7 X2 N
in large telecomm infrastructure company.
# e: @, z/ {: v' } A MSEE, or a PhD is preferred, with 10years of experience.
# |( n* Q, `* e. [/ J
3 t' E0 p. g; Y' t$ J% fSome portion of time will be spent in Shenzhen working with the HQ SI team. 2 o2 u J0 y: L3 I' u2 b) k
Travel will be about 30-60% to China./ z9 T3 i4 q7 {7 l: b
+ n* i h. j$ N# A/ q0 ?
Please contact mark.apton@xxxxxxxxxx
- I3 T+ x- @9 t4 g* W7 R; K! D3 t- h& E; S
插个广告，有符合以上条件，又愿意在深圳工作的人速速联系我 dbm@chinafastprint.com |
|
/1 
发表于 2013-4-26 22:19
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
发表于 2013-4-30 23:10