这个层次原理图为啥总报错呢？

winz

尝试画个层次原理图，很简单，就几个电阻一连，可是画完了DRC的时候总是报错：
3 e( K) R7 i% g) P- ^! ~Checking Misleading Tap connection
ERROR [DRC0039]   Tap may not be connected with the bus Check Entire net. DD1:  SCHEMATIC1, top  (3.55, 2.30)
ERROR [DRC0039]   Tap may not be connected with the bus Check Entire net. DD2:  SCHEMATIC1, top  (3.55, 2.30)
ERROR [DRC0039]   Tap may not be connected with the bus Check Entire net. DD3:  SCHEMATIC1, top  (3.55, 2.30)
ERROR [DRC0039]   Tap may not be connected with the bus Check Entire net. DD4:  SCHEMATIC1, top  (3.55, 2.30)
hierarchical pin name D[1..4],
bus name DD[1..4],
net alias 分别为DD1，DD2，DD3，DD4。
8 q8 |* e4 {1 U( b2 _问题出在哪呢？如果把根图上的bus name 去掉，就又报警了，
Check Bus width mismatch
N06946 has not connected with proper width
WARNING [DRC0030]   Bus width is not matching with the port Width block1,DD[1..4]:  SCHEMATIC1, top  (2.45, 2.30)
- C7 W" w4 W* _+ F  p$ Q6 K: l7 U1 KN06946 has not connected with proper width
WARNING [DRC0030]   Bus width is not matching with the port Width block2,DD[1..4]:  SCHEMATIC1, top  (3.55, 2.30)
9 ]; l1 @. }& E: B2 w$ h+ |! ~4 v