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标题: Hotfix_SPB16.50.002出来了，哪位大侠出手上传？ [打印本页]
作者: cxyjoe    时间: 2011-7-27 15:44
标题: Hotfix_SPB16.50.002出来了，哪位大侠出手上传？
本帖最后由 cxyjoe 于 2011-7-27 15:46 编辑 + E% w0 G8 s% P- j' p% {2 c+ j; u
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Hotfix_SPB16.50.002出来了，哪位大侠出手上传？+ k) ^( g  g& M1 z4 v7 V
http://www.nordcad.dk/dk/teknik__service/downloads/orcad_allegro_software_opdatering.htm: P9 ]# X' [# Q( a8 @4 l  B+ m9 u
作者: MentorUser    时间: 2011-7-27 16:45
Hey!! Thank you for the news!!!
作者: amaryllis    时间: 2011-7-27 17:00
补丁出的好快
作者: penny190    时间: 2011-7-27 18:11
又出囉～～真是快阿
作者: mengshang    时间: 2011-7-27 19:29
等待着下载
作者: interrupt    时间: 2011-7-27 22:54
还会不会异常退出啊
作者: biglin    时间: 2011-7-27 23:26
咳..太快了..
作者: rx_78gp02a    时间: 2011-7-28 07:44
期待，最近遇到铺铜的bug，希望能解决
作者: foxconnwj    时间: 2011-7-28 08:18
DATE: 07-24-2011   HOTFIX VERSION: 002
  e1 S9 _2 a! B/ Y# r# `- {7 c7 o* s===================================================================================================================================# I7 O! C* [6 ^' \& B
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE) v' O) F( A5 v/ l
===================================================================================================================================
) h9 n2 K2 u; y! z4 c, P527444  ALLEGRO_EDITOR EDIT_ETCH        Slide command needs to be enhanced for same net spacings
! q# W4 A9 @7 M! c# I583257  ALLEGRO_EDITOR EDIT_ETCH        Add Connect and slide command needs to be enhanced for same net spacings.6 |% q" \2 `! T- M4 S, Y
592956  ALLEGRO_EDITOR EDIT_ETCH        Same net traces will not push and/or shove each other.
' J* p2 T3 X5 B) \; o745285  ALLEGRO_EDITOR EDIT_ETCH        Requesting a true "shove" in Route > Slide for Same net routing.
+ M' Q/ |6 L/ V# @: p% [8 N) E773503  CAPTURE        OTHER            Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.  n/ {4 a4 c! D3 H- u; i1 h3 D; r
774270  F2B            PACKAGERXL       Require to ignore space in Pattern setting to prevent duplicated Refdes.7 Y1 q* q! F1 B! Q  {1 k
799984  ALLEGRO_EDITOR INTERACTIV       Enhance the Fix command to select just cline segs
' s+ ~+ C1 J/ b# `0 ~; X809008  CAPTURE        SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
! y4 g9 C5 ~# c" g* r* e7 [810058  CAPTURE        SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".& d: |1 s4 |6 |5 ]9 u' r$ t
821133  ALLEGRO_EDITOR MANUFACT         Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format! L1 p( o$ U7 V0 s! g
831710  CAPTURE        SCHEMATIC_EDITOR Capture adds extra junctions to design by itself6 f# i$ \' c! v
842410  ALLEGRO_EDITOR EDIT_ETCH        Ability to slide with "Shove" for "Same Net" segments/vias.% g5 s' Q; N/ s9 ?
854971  ALLEGRO_EDITOR INTERACTIV       Capability to add cline segment in a temp group
/ {$ ^2 M) `7 n. I7 d0 r860772  ADW            PCBCACHE         Save Shopping Cart (pcbcache) is crashing component browser7 Q: n- V2 \) @0 |7 z7 k
867842  CAPTURE        PROJECT_MANAGER  Capture crash with 'Open File Location"0 _3 c# w0 Z) k) A( `
868306  CAPTURE        CONNECTIVITY     mirror vertically removes junction creates extra nets
% i& y0 [, [2 D9 B7 I882677  EMI            RULE_CHECK       bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE4 ^, ]$ l0 s8 l( d+ E. h
891439  ALLEGRO_EDITOR INTERACTIV       moving cline segments
- p; L% V9 x! G# G2 P893544  ALLEGRO_EDITOR INTERFACES       IPC-D-356A netlist issue with BB vias.! }3 u$ T$ A0 ~
893765  ALLEGRO_EDITOR PARTITION        Mail command not sending out email on Linux platforms.
) b  s7 B  t. U" x3 n+ @0 ~1 k894390  SIP_LAYOUT     EXPORT_DATA      Generate all balls in the xml file for export to EDI's readPackage command+ V7 \# |% E! C1 R  I, O
895933  APD            DATABASE         Update Symbol shifts the center of the Dynamic Fillet and creating DRCs0 H, t. a, Y9 P! j' ]* @# u9 z
896598  ALLEGRO_EDITOR PLACEMENT        error message is misleading& b/ u" w0 J3 M" N2 n
897196  CIS            LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library5 u7 t, v3 @1 |% [( F4 s2 n. v
898598  ALLEGRO_EDITOR MENTOR           Negative planes from Mentor Board Station not being translated.6 M' W% _1 P: ~! F8 |3 o( O' Q# n
899556  ALLEGRO_EDITOR ARTWORK          Import artwork seems not to work correctly.
0 o$ m4 b) B4 ?7 [900501  ALLEGRO_EDITOR PLACEMENT        "Place Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5: ?* L1 D% w1 H# \" g3 N: w* J7 a
901141  CIS            EXPLORER         Japanese character appear garbled in CIS explorer window.0 S! _+ G# q( O2 w" J2 D$ y% a
901666  CAPTURE        OTHER            Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
; z# z5 b4 K( C6 g! b- K& w# y902066  ALLEGRO_EDITOR DRC_CONSTR       Shape in Region not follow the constrains3 H+ I: ^* O1 ~4 j9 s7 x9 `8 U
902349  CAPTURE        LIBRARY          Capture crashes while closing library9 r9 p3 C) v! B& V& L  R3 }5 Z
902508  F2B            PACKAGERXL       SPB16.5 Packager-XL consumes much more memory than 16.38 B2 B4 t6 w% h/ |) R0 p
902841  CAPTURE        GENERAL          Capture Start page does not show( P9 Y, i8 e) m) D% R* W2 X
902876  F2B            PACKAGERXL       Packager fails on the design upreved in 16.5
$ p5 i: L1 a/ E5 m4 X& V902959  CONCEPT_HDL    HDLDIRECT        HDLDirect Error while saving design1 U# J6 [5 H) O& u
903171  PSPICE         NETLISTER        Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?# H: {2 Y- }. w5 ]3 \& H+ x
903713  ALLEGRO_EDITOR PARTITION        Placement Replication do not work fine in the Design Partition
- T; h+ S# p/ r' V- J! B903799  SIP_LAYOUT     DIE_EDITOR       Disappear die pins after exiting co-design die editor4 h4 r; U2 k" d. F
904021  ALLEGRO_EDITOR OTHER            Export PDF from SPB 16.5 produces a file not text searchable
# B4 e4 j  [* x7 A! Z% B904339  CONCEPT_HDL    CORE             new design crashes using the attached CDS_SITE
: b$ J: z4 ?1 s  M: g( l* C904522  F2B            PACKAGERXL       Part will not package in 16.5  but packages in 16.3
, ]( o$ Y( k; V( g6 L904764  APD            OTHER            Enhance Scale Factor of Stream Out to support 4 decimal places
5 V: i7 k# P2 w9 M# s- f904771  ALLEGRO_EDITOR MANUFACT         Pin Number display issue.% M2 H: ~- q0 J# k6 B
904853  ALLEGRO_EDITOR GRAPHICS         Enhancement for showing Static shape as it was seen in 16.3
; L6 q2 \$ I6 f905144  CONSTRAINT_MGR ECS_APPLY        Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM0 v% I2 y9 f; |
905314  F2B            PACKAGERXL       Import physical causes csb corruption
+ W$ R, j3 z7 @3 }. R& q905337  CONCEPT_HDL    CORE             ConceptHDL crashes after Import Design process.0 f5 b5 c3 t; z! s* _. F  J' z
905533  ALLEGRO_EDITOR INTERACTIV       Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible5 g& [7 A' t" |  X
905796  CONCEPT_HDL    CONSTRAINT_MGR   Fujitsu CM issue inaccurate concept2cm diff pair issues
$ r" R% P, @) O0 ^5 `$ A905811  CAPTURE        EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid- ~( E8 W7 g9 |3 F+ w1 v
906118  CONCEPT_HDL    CONSTRAINT_MGR   Cannot open CM if SIGNAL_MODEL value was not assigned in ptf., H; B1 f6 r2 |- n: W
906153  ALLEGRO_EDITOR SCRIPTS          Unable to run allegro script in batch mode on the attached board.
2 F) f' x% B/ d, h906182  APD            EXPORT_DATA      Modify Board Level Component Output format
1 J& k8 A% e2 z( I1 l$ B2 Z8 Y1 f906200  ALLEGRO_EDITOR DFA              Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element
( {/ k. S* b9 f906517  PSPICE         PROBE            PSpice new cursor window shows incorrect result.6 @3 I# Q8 O2 P/ d# [, E
906627  ADW            COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.- Y5 F  o0 L- }
906647  SIG_INTEGRITY  LIBRARY          lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run% ^5 U7 y: G7 H+ S9 |
906673  F2B            PACKAGERXL       Ignore the signal model validity check during packaging; o4 M: E- |& `, L9 F7 N2 }
906688  ADW            LRM              A copy of source design gets created in worklib of target design after 'Import Design'0 ?# K( ]: {9 s
906750  ALLEGRO_EDITOR PARTITION        Importing design partition removes the testpoint reference designation# C; o1 C& G1 S1 Y* L$ S% s( L
906874  PSPICE         NETLISTER        Error less than 2 connections for unconnected hierarchical pin0 X1 \- y7 R9 |, f; e
907095  F2B            OTHER            Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used" s1 P! o' F( v2 e# C7 x
907424  ALLEGRO_EDITOR GRAPHICS         Allegro add option for pre 16.5 shape display
% s2 I- z/ ]0 @3 \9 j907490  CAPTURE        NETLIST_LAYOUT   16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.3 |# o, t6 V& K3 u( d4 [' k7 n
907884  SIP_LAYOUT     MANUFACTURING    Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
8 O/ O! z4 L  Q( f907885  SIG_INTEGRITY  OTHER            Matchgroup targets lost when importing netlist  to Allegro layout in HF31( O1 t1 i- o$ L4 Y
907929  CAPTURE        TCL_SAMPLE       TCL command to delete a property from parts in a library is not working correctly: C8 j- h4 J0 d/ O) a
907933  SIG_INTEGRITY  OTHER            Single line impedence not working in OrCad PCB Professional
) U8 {1 ]0 u% l, v$ X1 r( f907963  CONCEPT_HDL    CORE             Design uprev issue when moving from 16.2 to 16.5& m3 ?, f5 I% B/ c- R
908000  SIG_INTEGRITY  OTHER            Inconsistence z-axis delay reported on Tpoint when define at via location.- w3 h7 h( g6 O* [* j
908057  CONCEPT_HDL    CORE             DE HDL crash with the cut and paste of a signal name$ s! ]' v) n3 g* g! b. `) e  `
908060  CONCEPT_HDL    CORE             CTRL+LMB Option not working correctly in 16.3
  Z% Q0 H$ m& ~) c! Z: w- E0 T908210  CAPTURE        CONNECTIVITY     Connection is being lost while dragging a component9 k& H/ E4 i3 i- M0 F
908241  CAPTURE        DRC              DRC error column is blank in DRC markers window in 16.5" f: \3 V7 ?( Y2 G( j3 t8 `7 |
908339  RF_PCB         BE_IFF_IMPORT    mechanical holes VIAFC are not at the right place
; _  J) u- s' j2 X908534  SIP_LAYOUT     SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays
1 V/ U& Q8 K9 o- I9 ~! S: A7 w* e908535  F2B            DESIGNVARI       When I try to view my variant file the variant editor crashes; K+ z! A+ ?% v& m4 R  D& v
908595  APD            3D_VIEWER        Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b+ x8 z0 {1 A7 t& D, N$ }  c
908849  CAPTURE        ANNOTATE         Getting crash while annotating the attached design
. u+ T5 o8 f: D) C908874  CONCEPT_HDL    CORE             Part Manager - No Part Found error when using CCR# 775788 feature: G- l8 o, d8 g5 j! D4 e
909077  CONCEPT_HDL    CORE             After packaging pin numbers remains invisible even when $PN
" A% F3 _% x& ]' P; P) }909104  ALLEGRO_EDITOR SYMBOL           Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.; U# U, ~8 F" Z/ C! V4 h
909417  ALLEGRO_EDITOR REPORTS          "report -v upc" returns 'Segmentation fault' on Linux& S& K- y3 Q! c- @3 \" K
909635  SIP_LAYOUT     DIE_STACK_EDITOR Add Interposer crashes in SiP Layout0 w7 d- G# _2 s6 c+ q$ w% U
909749  ALLEGRO_EDITOR MANUFACT         Allegro Crash during dimensioning6 f8 T4 E1 d$ O7 t% d: T
909760  SIP_LAYOUT     MANUFACTURING    Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
$ U- d. C1 h" G909861  F2B            PACKAGERXL       NetAssembler broken within the latest 16.30.0319 a# ]* i+ Y6 U/ o$ y4 ]
910006  CONCEPT_HDL    INFRA            Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.7 W2 j$ m$ D1 F- p
910141  CAPTURE        NETGROUPS        Modify NetGroup definition does not update Offpage Connector2 o" z5 r7 K  V8 e% c
910340  ADW            LRM              Import design in schematic, only 1 page import,  the entire block is getting imported.
5 D& c8 `; q2 e4 k# S3 @9 q910678  SIG_INTEGRITY  OTHER            The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
% W- F9 d, V9 X3 X' X910713  F2B            DESIGNVARI       Variant Editor crashes when you click web link under ?hysical Part Filter?window.
8 _7 c6 R# Y0 _5 _+ W910936  F2B            PACKAGERXL       ConceptHDL subdesign net name is inconsistent
/ G- j% J2 o/ E. m  l$ W4 d, |911530  ALLEGRO_EDITOR SYMBOL           Package Symbol Wizard does not create symbol with the name given
& F. {( Y7 Y7 y" d; ^$ `911631  CONCEPT_HDL    CORE             DEHDL crashes when opening a design: Z: Z3 ]5 C! y" \* ?$ y+ a
912001  ALLEGRO_EDITOR OTHER            option_licenses entries are made in allegro.ini even when not set as default& e. u% G) K: D3 \$ O
912459  F2B            BOM              BOMHDL crashes before getting to a menu
5 V8 x0 z9 \& I: m; @& f9 r1 U913359  APD            MANUFACTURING    Package Report shows incorrect data
- W5 h' V% ?7 I- E0 y下载完了，安装中
作者: cxyjoe    时间: 2011-7-28 08:38
楼上的大侠共享一下啊
作者: text108    时间: 2011-7-28 09:13
foxconnwj大侠共享一下啊
作者: 每天学一点    时间: 2011-7-28 13:23
好快呀
作者: fangqwas    时间: 2011-7-28 13:36
快...
作者: suiwinder    时间: 2011-7-28 14:41
foxconnwj 发表于 2011-7-28 08:18 - n/ E% S# I! c. j
DATE: 07-24-2011   HOTFIX VERSION: 002
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如果可以共享就和大家分享下，如果不能就不要说风凉话！
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作者: hzqydq    时间: 2011-7-28 14:46
希望大家共享一下
作者: bluemare    时间: 2011-7-28 14:57
又出囉～～真是快阿
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作者: gn165625076    时间: 2011-7-28 22:55
本帖最后由 gn165625076 于 2011-7-28 22:55 编辑 , e. l  \6 `$ ~$ Z& \- M2 j6 V
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迅雷离线下载一天了，还是0%
作者: cxyjoe    时间: 2011-7-29 07:49
本帖最后由 cxyjoe 于 2011-7-29 07:49 编辑
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回复 gn165625076 的帖子) ?' G, n# r8 ~& H6 M
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这个貌似用迅雷是下不来的。。。
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作者: cxt668    时间: 2011-7-29 08:19
没必要更新的那么快吧！
作者: coyoo    时间: 2011-7-29 09:24
先搞清楚为什么要打补丁吧？
作者: cxyjoe    时间: 2011-7-29 09:46
喜欢打的就打，不喜欢打的就不打，不就完了
作者: laoma311    时间: 2011-7-29 10:34
哪儿能下，各位大侠
作者: suiwinder    时间: 2011-7-29 10:44
告诉个能下的地方吧
作者: longzhiming    时间: 2011-7-29 10:58
补丁出得快说明问题严重,问题多,这是坏消息啊,Cadence开始学AD的了，新版出得快，然后就是打一大堆补丁，，，，没什么好高兴的。
作者: cxyjoe    时间: 2011-7-29 11:28
cadence一直就是每个月出一个补丁，没什么快不快的啊
作者: laoma311    时间: 2011-7-29 14:08
哪儿能下，各位大侠？十分感谢！！！0 ]& h+ O$ _3 K+ |
作者: rainbowII    时间: 2011-7-30 17:32
已经共享了，注意观察
作者: xibuol    时间: 2011-7-31 20:09
http://u.115.com/file/aq7j2itn
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