|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
大家好，以前用AD6,PADS, 与在用SPB16.2,很不习惯呀。
0 t( T1 x( a: j) o, g4 J4 E/ m 在做完原理图，DRC检查没有错误后，生成网表时，出现：0 W8 _: M! E6 R% I, R: }
#248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'. Each section must have at least one non-common pin.! v6 ]2 M8 [9 B! F
Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.
* z' e! Q# z" ]5 D2 }- D" X0 T 我检查了原理图SYMBOL和PCB封装，也换另外的PCB封装试了试，错误依旧。
/ o$ r; z7 V) |) B 大家帮我看看，是什么原因呀。, }6 ]* z6 i3 ]. _/ C' A/ | m
我在画原理图时还碰到其它的问题：: C$ m' r# J8 s* e( N
1：元件编号如电阻电容之后，总自动出现一个A或是B, 如：R120A . W# K0 K8 H, U/ U! w
2: 在COPY一个元件到另外一个地方去时，本应每COPY一次编号都自动增加，可现在是每COPY两次，编号才自动增加一次。7 v m9 e) H# n; I
原理图工程我加在附件里了，大家可以打开F3文件帮我看看。) v% `; W$ W% T c0 x" Q4 {; d
为方便大家检查，我把生成网有的出错贴在下面了：% [4 j% j r& y
********************************************************************************
$ o0 c& i+ d, y( D% | T# ZDesign Name:
* Q3 L7 [- m' p" y9 Z3 I FE:\Hi3515FJ_CADENCE\hi3515fj.dsn
; s7 O3 o h; o+ w: w9 tNetlist Directory:6 X; e5 z( D1 Q* y* U4 \/ o3 z2 `0 ~
E:\HI3515FJ_CADENCE\NETLIST
7 u1 p2 ^. ~/ I6 H9 _( j, FConfiguration File:
# z; {2 q9 J) ND:\Candence\SPB16.2\tools\capture\allegro.cfg
7 ~$ x) Q% Q1 aSpawning... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint" ]: E& O6 p5 X/ }, u! ]+ F1 P
#1 Warning [ALG0016] Part Name "PHONE JACK-4_0_PHONEJACT_4_PHONE JACK-4" is renamed to "PHONE JACK-4_0_PHONEJACT_4_PHON".
8 R6 I' M0 ^# ~8 E- N* r2 N#2 Warning [ALG0016] Part Name "SN74CBT16214_0_SOP56-20-250-550_SN74CBT16214C" is renamed to "SN74CBT16214_0_SOP56-20-250-550".: ^3 S( x% Z/ q. z. V, t8 W2 T' U
Scanning netlist files ...' A( w0 t" v! K; Z B& ?
Loading... E:\HI3515FJ_CADENCE\NETLIST/pstchip.dat
0 T6 P* K) q F/ ?. q#248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'. Each section must have at least one non-common pin.
% v! m8 H" l3 f1 X* A( H Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.4 Y5 D5 }$ Q2 L. n' ?0 T
ERROR(SPCODD-47): File E:/HI3515FJ_CADENCE/NETLIST/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again.
/ K* d+ a# F: k4 t. h) D1 S h#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schema+ p; i( V( H8 Q' p( m
tic and rerun packaging.
$ D+ Q! ]- \4 c# ~& k#3 Error [ALG0036] Unable to read logical netlist data./ C& ~% g9 M c( _5 |
Exiting... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
6 W5 z! Z, U e$ J) \9 C w C+ J1 o& ]- l* Y+ u; h# h
*** Done *** |
|
|
/1 
发表于 2011-6-12 12:00
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！