Orcad capture生成网表时出错，大家帮我看看

lyf9908

大家好，以前用AD6,PADS, 与在用SPB16.2,很不习惯呀。 . N! D1 Z* K$ n9 Q+ F# f% `     在做完原理图，DRC检查没有错误后，生成网表时，出现：    #248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'.  Each section must have at least one non-common pin.         Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.       我检查了原理图SYMBOL和PCB封装，也换另外的PCB封装试了试，错误依旧。   大家帮我看看，是什么原因呀。 . ]' l% Q7 P/ z    我在画原理图时还碰到其它的问题：       1：元件编号如电阻电容之后，总自动出现一个A或是B,  如：R120A - j9 ~, D5 e1 S; i3 M3 @0 H; Z      2: 在COPY一个元件到另外一个地方去时，本应每COPY一次编号都自动增加，可现在是每COPY两次，编号才自动增加一次。      原理图工程我加在附件里了，大家可以打开F3文件帮我看看。 6 T, w2 l( ^9 }1 b$ w- q, W& D% c5 k2 X     为方便大家检查，我把生成网有的出错贴在下面了： 0 O; s$ ?$ R8 X' x      ******************************************************************************** Design Name: % x: F" O# ^7 X4 ^) aE:\Hi3515FJ_CADENCE\hi3515fj.dsn Netlist Directory: 9 |0 \- o. t7 d5 V. K$ k5 S5 [$ xE:\HI3515FJ_CADENCE\NETLIST ; i( Q/ [5 v5 E5 C% h7 J- y; j; f& OConfiguration File: ' u9 q3 R1 x& x5 O" Q/ H7 ~, ]$ ZD:\Candence\SPB16.2\tools\capture\allegro.cfg 1 l/ ^/ n3 c6 F. }3 GSpawning... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint" ' U! R6 ]& n: w# b/ h" Z#1 Warning [ALG0016] Part Name "PHONE JACK-4_0_PHONEJACT_4_PHONE JACK-4" is renamed to "PHONE JACK-4_0_PHONEJACT_4_PHON". / a' d8 g" ~8 @  Y0 W0 w#2 Warning [ALG0016] Part Name "SN74CBT16214_0_SOP56-20-250-550_SN74CBT16214C" is renamed to "SN74CBT16214_0_SOP56-20-250-550". Scanning netlist files ... # W, S  H- J6 \% k( a* I  D" yLoading... E:\HI3515FJ_CADENCE\NETLIST/pstchip.dat #248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'.  Each section must have at least one non-common pin.         Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part. ' ?: g- Z3 G9 N0 g6 R              ERROR(SPCODD-47): File E:/HI3515FJ_CADENCE/NETLIST/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again. #53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schema tic and rerun packaging. #3 Error   [ALG0036] Unable to read logical netlist data. Exiting... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint" 2 F7 g# ^5 f* d# Q0 ^ *** Done ***