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PCB Designer’s si guide

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发表于 2008-5-26 11:07 | 只看该作者 回帖奖励 |正序浏览 |阅读模式

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PCB Designer's SI GUIDETable of Content
  p% h4 E6 ?+ B9 q# ZBasics of SI___________________________________________________________________5
9 Y- ?2 K% }) S7 D5 K" `- j% Q1.1 When Speed is important? _____________________________________________5
" v$ S# X/ |3 Q% y: d1.1.1 Acceptable Voltage and timing values ________________________________5
/ d# P& g1 @" }# L! N+ Z" O2 R3 W0 c1.2 Signal Integrity ______________________________________________________5 ! @+ d9 O0 c- f2 H3 H( Y/ E
1.2.1 Waveform Voltage Accuracy _______________________________________5
2 P; D; Z' W# y1 g1.2.2 Timing_________________________________________________________5
1 z3 e5 ^5 N6 w" S9 ]0 h+ P) q/ R1.3 Speed of currently used logic families ____________________________________5 % A2 ?3 H! Z4 o  s
1.3.1 Transition Electrical Length (TEL) __________________________________6
# P6 ?8 P2 s$ o, n2 a1.3.2 Critical length ___________________________________________________6 ; k) X4 o( T: Z- K; r2 _+ h" |) W
1.3.3 What is Transmission Line? ________________________________________6 . k  z& P2 p. b  Z4 ~3 z
1.3.4 What is moving in a Transmission line?_______________________________6
% x" k5 Z& t+ F0 ~1.3.5 Power Plane Definition____________________________________________6 8 J7 H% N! Y) V! ~& w7 f
1.3.6 The concept of Ground ____________________________________________7
( r, F4 ^: i. \; y) |* w) S( S1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
4 R+ b& f3 c6 [1.5 RLC Transmission Line Model _________________________________________8
# c% b; Y- D( W( {9 S" x1.5.1 What is Impedance? ______________________________________________8
( e7 K. b7 w4 F" {% s9 A1.5.2 A Practical impedance equation for microstrip _________________________8
% s/ p0 r4 N/ w. i( q1.5.3 What is relative dielectric constant Er? _______________________________9 ; X, p& h3 O1 x- f# C
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2 Interconnections for High Speed Digital Circuits _______________________________10
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2.1.1 Summary______________________________________________________10
* T; D* p$ M2 @+ `2.2 Examples of dynamic interfacing problems _______________________________10
3 b6 H5 f4 `% z0 d6 C  {2.3 IC Technology and Signal Integrity _____________________________________12
- Y4 t- h* I4 c2.4 Speed and distance __________________________________________________14 ) J9 d! T- N& Y
2.5 Digital signals: Static interfacing _______________________________________15 . D6 s& L# U8 H
2.6 Digital signals: Dynamic interfacing ____________________________________16 7 O5 k/ _7 m1 y( d  j" D9 [$ {
2.7 Review questions ___________________________________________________18 , b: C/ A3 b6 q1 x; g
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3 Interconnection Models____________________________________________________20
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3.1 Summary__________________________________________________________20 ' q- |9 Y" C' V5 u; P0 v
3.2 Reference model for interconnection analysis _____________________________20
! I# r; `9 J; R3 r3.3 Receiver model_____________________________________________________21
! U2 y7 e. ]* g( E8 Z$ M& o& `  e3.4 RC interconnection model ____________________________________________23 ' S4 W' L) |5 r- H2 ]
3.5 Parameters of the interconnection ______________________________________25   v) ?* `3 t3 L: m
3.6 Refined models _____________________________________________________26
0 Z1 ~! |( L3 t0 A6 E3.7 Review question ____________________________________________________28
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4 Transmission Line Models _________________________________________________31
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4.1 Summary__________________________________________________________31
' Q* w2 ~! V! g, _4 j4.2 Transmission line models _____________________________________________31 5 z; y8 Y" i( ?2 @( d/ w; ~! r
4.3 Loss-less transmission lines ___________________________________________32
5 P7 q# H% L4 x5 p8 G4.4 Critical Length _____________________________________________________34
/ d. w3 O, I' J, Z( I4.5 Reference transmission line model______________________________________35 - H1 l* W* e* ?8 u, N- R: D  ~1 _
4.6 Line driving _______________________________________________________36
! o+ Y3 e1 d- p4 W4 d3 x4.7 Propagation and reflected waves _______________________________________37
+ K1 H, t5 M9 V5 u4.8 A sample system____________________________________________________39
* |; G& M  j2 F; u4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45
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5.1 Summary__________________________________________________________45 * b: I) `7 a* y. P
5.2 Transmission time and skew___________________________________________45 ) u8 Y5 I7 Q! {" l) n
5.3 Effects of termination resistance _______________________________________46 5 v6 E' j- o# B1 W
5.4 Lattice diagram _____________________________________________________48
, H& j$ z4 }5 K3 F5.5 Examples of Real Lines ______________________________________________49
8 L/ u3 C, c1 C* n! ?3 ~5.6 Simulation code ____________________________________________________51 ' e& ?1 ?& e& s
5.7 Examples of results__________________________________________________54
( T5 g, x4 a) C$ A& ]5.8 Review questions ___________________________________________________55
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6 Design guide for interconnection ____________________________________________57
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6.1 Summary__________________________________________________________57 % g- V7 U5 _- [
6.2 Incident wave switching ______________________________________________57   F" H+ X% i; V1 }1 }2 L
6.3 Effects of capacitive loading __________________________________________58 0 K7 K* Q# q3 r" h  ]0 `
6.4 Termination circuits _________________________________________________59 / E2 x: C: e# p( V6 u. O; t
6.4.1 Passive termination______________________________________________60
% @2 D( \: q- K. v; Z6.4.2 Low power termination___________________________________________61
- V9 _& u2 [& n! {' l6 t7 ]  s6.4.3 Active low power termination circuit. _______________________________61
$ Z2 Z: X8 s) S# B) b6 W0 O6.5 Driving point-to-point lines ___________________________________________62
4 Y5 Z0 A) y& J8 l: @6.6 Driving bused lines __________________________________________________64
1 m' B- x5 t6 D6.7 Design guidelines ___________________________________________________67
4 K' x8 i1 G5 I( e$ Y1 R6.8 Review questions ___________________________________________________67

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发表于 2008-5-26 16:33 | 只看该作者
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 楼主| 发表于 2008-5-26 11:09 | 只看该作者
Signal Integrity in Digital Circuits ___________________________________________70
# B* d! A% v  G! }" N& L; e& Q" }7.1 Crosstalk __________________________________________________________70
& S% e6 |7 P4 }; \1 _7.1.1 Summary______________________________________________________70 2 W2 P) H0 v5 L$ h# `5 c: A+ Z9 G
7.2 Examples of signal integrity problems ___________________________________70 2 `. F' Y( C: D0 C- w$ B' g8 k& O
7.3 Simplified Model for Crosstalk Analysis _________________________________71 $ Z* I8 n# V0 B7 s- ]2 F
7.4 Forward and backward crosstalk _______________________________________74
0 V5 F) p2 L3 P7 H7.5 Examples__________________________________________________________76 * ?1 R3 `+ {& z2 s% V
7.6 Near-end and Far-end crosstalk ________________________________________80 * O* g0 ~' R* S4 Y# r/ m: K" O
7.7 Review questions ___________________________________________________81
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8 Design Guide to Handle Crosstalk ___________________________________________85

! `% ~& ?' l/ @& P* E8.1 Summary__________________________________________________________85 1 ]# A% F, k+ j9 }. K! k
8.2 Effects of Crosstalk __________________________________________________85 ! p, @0 v8 `6 V, ^/ ?
8.3 Passive countermeasures _____________________________________________86 ) h( u. ^# o$ r
8.4 Active Control of Crosstalk ___________________________________________92 $ C1 F3 ~8 g' V/ N, S, N0 _
8.5 Review questions ___________________________________________________94
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9 Ground Bounce and Switching Noise_________________________________________97

" V8 [; U0 p6 Q9.1 Summary__________________________________________________________97 4 R) _/ n2 F+ E6 L
9.2 The totem pole Current Spike__________________________________________97 2 E" V, l$ X% r
9.3 Current flow in the output capacitance __________________________________100
9 c8 C2 n0 I. m7 \9.4 Total Ground Bounce _______________________________________________100
: a. c2 t; S# Z9 D  S9.5 Review questions __________________________________________________105 6 `3 L* U" \, b* L
10 Design Guide for Ground & Power Distribution _____________________________107
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10.1 Summary_________________________________________________________107
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PCB Designer’s SI Guide Page 3 Venkata

9 m# O5 F; m  L& ^6 z0 B/ Y' ~8 R! }10.2 Decoupling Capacitors ______________________________________________107
6 t: B9 A* |& ?) g/ R. ?, _10.3 Placement of bypass Capacitors _______________________________________113
- V& r# t+ X& ]- s' w. q& O10.4 Ground and power distribution________________________________________114
+ N$ V6 H7 m" K10.5 Clock distribution __________________________________________________115
' A5 r* u$ ?- |. g10.6 Review Questions __________________________________________________118
# J# P" B) ]. G% q# T0 n. K0 t1 J11 Laboratory Experience _________________________________________________120
* C* A) `; e3 d, R/ D) }0 W11.1 Summary_________________________________________________________120 : A4 Q- K  ~0 l+ v
11.2 Aim of the experience_______________________________________________120
. V4 ]8 M; W: A' w11.3 Generator Parameters _______________________________________________122
, w! W( I' t% |3 }5 @11.4 Cable Parameters __________________________________________________123 5 S$ b" h9 g: c9 h, Y
11.5 Mismatch at driver and at termination __________________________________124
9 j8 i( c7 Z+ @2 J& b11.6 Capacitive Load ___________________________________________________125
6 |1 L. i* ?) Q% n4 c9 P' a4 b11.7 7. Time-domain reflectometer ________________________________________127
# k' r  h. F( Y2 f+ t11.8 Driving the line with logic devices _____________________________________128
; G% c" n% _  v6 I2 [2 ?" R12 SI Analysis Strategy____________________________________________________133 3 Z  E' `, H7 b' \
12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133 - S: u& j; d6 v6 f
12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
+ E/ e7 C& f' D7 k7 [1 _; m3 @12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
3 a5 y1 D2 P' B3 Z12.3 SOLUTION SPACE ANALYSIS _____________________________________135
# O5 r& O( R9 F1 O* j12.3.14 c6 }0 `: z% N: ~% `$ y
STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
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12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135 2 S' A+ T  ^# {8 K' `! d* n
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STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136

8 }+ [% ?( F: F# o3 y12.3.4
1 v( s% K+ H9 K! d( q$ }7 E- gSTEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
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12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
; W" c& P. C+ K7 r0 E# M: F3 ?12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
, o3 J. s" n) I: u: h12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
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STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137

( _8 b! l! F# K$ s7 _2 P, z12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
5 X! p8 q/ k/ I( E" i: c12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139   K+ W, D. l) H, o: `: V# _  ^( a
12.4 CONCLUSION____________________________________________________139 2 K1 g# p: k, G3 G& l# m
13 Glossary _____________________________________________________________141
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PCB Designer’s SI Guide Page 4Venkata
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