PCB Designer’s si guide

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PCB Designer's SI GUIDETable of Content
Basics of SI___________________________________________________________________5
1.1 When Speed is important? _____________________________________________5
1.1.1 Acceptable Voltage and timing values ________________________________5
1.2 Signal Integrity ______________________________________________________5
! D8 |9 b; f) c, I5 J: j6 `1.2.1 Waveform Voltage Accuracy _______________________________________5
: E# C; t0 U0 `" t( `1.2.2 Timing_________________________________________________________5
1.3 Speed of currently used logic families ____________________________________5
1.3.1 Transition Electrical Length (TEL) __________________________________6
% z& A2 v# Q0 [1 s1.3.2 Critical length ___________________________________________________6
- r! s& [! C8 E. _1.3.3 What is Transmission Line? ________________________________________6
1.3.4 What is moving in a Transmission line?_______________________________6
1.3.5 Power Plane Definition____________________________________________6
9 t7 u+ X& A' h1.3.6 The concept of Ground ____________________________________________7
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
1 d1 w  R2 l8 h  n1.5 RLC Transmission Line Model _________________________________________8
' a6 d/ s- J2 m0 r+ P- U' [1.5.1 What is Impedance? ______________________________________________8
1.5.2 A Practical impedance equation for microstrip _________________________8
7 D: }0 ?6 x! W$ h7 m0 L2 Z1.5.3 What is relative dielectric constant Er? _______________________________9

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2 Interconnections for High Speed Digital Circuits _______________________________10

5 @3 i" _( |" t" Y( P% `) O5 G2.1.1 Summary______________________________________________________10
2.2 Examples of dynamic interfacing problems _______________________________10
& d8 ^/ G9 Q; r& f2.3 IC Technology and Signal Integrity _____________________________________12
2.4 Speed and distance __________________________________________________14
& ?- O* e' ~' Y& Q+ D9 i2.5 Digital signals: Static interfacing _______________________________________15
2.6 Digital signals: Dynamic interfacing ____________________________________16
- Y( k4 H$ J. p9 J3 c) T/ Y: ?2.7 Review questions ___________________________________________________18
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3 Interconnection Models____________________________________________________20

! W+ C6 R0 b1 `, f3.1 Summary__________________________________________________________20
3.2 Reference model for interconnection analysis _____________________________20
  R& ^& X+ ~- d2 |/ f3.3 Receiver model_____________________________________________________21
3.4 RC interconnection model ____________________________________________23
1 G3 L; ]: d2 h3.5 Parameters of the interconnection ______________________________________25
3.6 Refined models _____________________________________________________26
- y% T# _4 O9 z* ~% ^3.7 Review question ____________________________________________________28
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4 Transmission Line Models _________________________________________________31

4.1 Summary__________________________________________________________31
2 L4 d% E$ E' h4 G1 f/ U4 x0 f4.2 Transmission line models _____________________________________________31
' r3 L" A; S6 h5 f: O' j4.3 Loss-less transmission lines ___________________________________________32
4.4 Critical Length _____________________________________________________34
2 P* }2 Z/ e8 \" q" q, w+ A0 }5 a9 p4.5 Reference transmission line model______________________________________35
4.6 Line driving _______________________________________________________36
( m8 C8 h# K1 \- r: x7 ]4.7 Propagation and reflected waves _______________________________________37
# n! u) l/ l: |4.8 A sample system____________________________________________________39
4 b$ W9 F0 |' p4.9 Review questions ___________________________________________________42

PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45

) C( o& L0 b% N  v; {5.1 Summary__________________________________________________________45
2 t" Q% |7 v! W3 \1 e5.2 Transmission time and skew___________________________________________45
5.3 Effects of termination resistance _______________________________________46
- N+ b7 W9 c, ~% {. X- {5 ?5.4 Lattice diagram _____________________________________________________48
5.5 Examples of Real Lines ______________________________________________49
0 X& C! S3 B8 C5 C3 ?0 ?) d/ N5.6 Simulation code ____________________________________________________51
/ ~. w8 E; u5 V0 k3 Z3 M5 W5.7 Examples of results__________________________________________________54
% }# b+ ?1 @, S$ Q& i# t5.8 Review questions ___________________________________________________55
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6 Design guide for interconnection ____________________________________________57

& N9 c0 I0 V9 ~9 J6.1 Summary__________________________________________________________57
/ B' S9 t+ F, b9 P1 [6.2 Incident wave switching ______________________________________________57
6.3 Effects of capacitive loading __________________________________________58
8 i9 e9 D! m  z8 H4 y$ [. m. V2 Y% D6.4 Termination circuits _________________________________________________59
6.4.1 Passive termination______________________________________________60
8 J1 e+ b- S) U0 a! R  T' V6.4.2 Low power termination___________________________________________61
6.4.3 Active low power termination circuit. _______________________________61
6.5 Driving point-to-point lines ___________________________________________62
5 {- z2 ?4 Y  i" q( Y& W  O/ |+ v" v, {1 u6.6 Driving bused lines __________________________________________________64
/ d# o) K* q7 x! C' O% N6.7 Design guidelines ___________________________________________________67
6.8 Review questions ___________________________________________________67

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Signal Integrity in Digital Circuits ___________________________________________70
+ Z; B/ C  |; K4 d! m$ y) i9 \7.1 Crosstalk __________________________________________________________70
5 X. T: e/ Y/ H6 `/ n7.1.1 Summary______________________________________________________70
8 ]" F8 t/ B9 I' a# H7.2 Examples of signal integrity problems ___________________________________70
7 V4 l+ }) _- F/ s2 E: _7.3 Simplified Model for Crosstalk Analysis _________________________________71
7.4 Forward and backward crosstalk _______________________________________74
7.5 Examples__________________________________________________________76
7.6 Near-end and Far-end crosstalk ________________________________________80
% v9 O: g* H% o2 Z3 H0 _7.7 Review questions ___________________________________________________81
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8 Design Guide to Handle Crosstalk ___________________________________________85

8.1 Summary__________________________________________________________85
8.2 Effects of Crosstalk __________________________________________________85
8.3 Passive countermeasures _____________________________________________86
8.4 Active Control of Crosstalk ___________________________________________92
8.5 Review questions ___________________________________________________94

9 Ground Bounce and Switching Noise_________________________________________97

9.1 Summary__________________________________________________________97
0 S; R+ |0 W$ [9.2 The totem pole Current Spike__________________________________________97
6 \; f* f7 u) O+ P, |4 Q7 _9.3 Current flow in the output capacitance __________________________________100
9.4 Total Ground Bounce _______________________________________________100
/ x. I0 U( D" B. s, m9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107

10.1 Summary_________________________________________________________107

PCB Designer’s SI Guide Page 3 Venkata

10.2 Decoupling Capacitors ______________________________________________107
10.3 Placement of bypass Capacitors _______________________________________113
10.4 Ground and power distribution________________________________________114
8 l2 _5 p- Z/ F# M6 ?/ X10.5 Clock distribution __________________________________________________115
" Z; l/ w6 s7 `/ j  a10.6 Review Questions __________________________________________________118
7 D6 ?* h6 E, l2 p5 a+ X5 X11 Laboratory Experience _________________________________________________120
9 T0 N9 |/ L; R/ S% _/ P11.1 Summary_________________________________________________________120
11.2 Aim of the experience_______________________________________________120
! l' @5 z1 ^. J8 T. b* f. {) _11.3 Generator Parameters _______________________________________________122
& @2 {+ `& \2 s0 Q11.4 Cable Parameters __________________________________________________123
11.5 Mismatch at driver and at termination __________________________________124
11.6 Capacitive Load ___________________________________________________125
11.7 7. Time-domain reflectometer ________________________________________127
11.8 Driving the line with logic devices _____________________________________128
+ Z+ P6 U$ K* C7 M12 SI Analysis Strategy____________________________________________________133
12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
12.3 SOLUTION SPACE ANALYSIS _____________________________________135
12.3.1
! a/ D7 W. ]7 C" P# L: s9 ZSTEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
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; T# J/ n7 j# n6 v6 tSTEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
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1 B; G: ^$ E- U) n0 c0 g8 rSTEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
5 x- p. S% _. h12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
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STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
# ]6 o. ^- H& n- H12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
; ~0 [+ L& J9 X9 k! P# z2 V* i12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
" e: m1 d; |8 G, I- Y2 P1 L7 s12.4 CONCLUSION____________________________________________________139
13 Glossary _____________________________________________________________141

PCB Designer’s SI Guide Page 4Venkata