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标题:
SPI程序问题
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作者:
jiaohuang2004
时间:
2011-3-19 05:12
标题:
SPI程序问题
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity spi is
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port
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(
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reset : in std_logic; --global reset signal
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sysclk : in std_logic; -- systerm clock
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data_in : in std_logic_vector(13 downto 0);
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spi_o : out std_logic;
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sck_out : out std_logic;
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ss_n : out std_logic_vector(1 downto 0)
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);
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end spi;
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architecture b of spi is
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type state_type is (idle,shift,stop); -- data type define
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signal state : state_type;
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signal out_reg : std_logic_vector(13 downto 0):=(others=>'0');
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signal clkdiv_cnt : std_logic_vector(3 downto 0) :=(others=>'0');
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signal bit_cnt : std_logic_vector(3 downto 0) :=(others=>'0');
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signal sck_o : std_logic;
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signal full : std_logic;
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begin
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sck_out <= sck_o;
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process(sysclk)
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begin
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if (sysclk'event and sysclk = '1') then --reset
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if (reset = '1') then
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ss_n <= (others=>'1'); --AD5553 idle CS =1
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out_reg <= (others=>'0');
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clkdiv_cnt <= (others=>'0');
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bit_cnt <= (others=>'0');
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spi_o <= '1';
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sck_o <= '0'; -- AD5553 SCK idle is 0
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state <= idle;
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full <= '0';
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else
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if(full = '0') then
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out_reg <= data_in ;
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full <= '1';
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end if;
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case state is
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when idle =>
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state <= shift;
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spi_o <= out_reg(13);
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out_reg <= out_reg(12 downto 0) & '0';
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sck_o <= '0';
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when shift =>
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clkdiv_cnt <= clkdiv_cnt + '1';
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if (clkdiv_cnt(2 downto 0)="111") then
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sck_o <= not sck_o;
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end if;
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if (clkdiv_cnt = "1111") then
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spi_o <= out_reg(13);
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out_reg <= out_reg(12 downto 0) & '0';
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bit_cnt <= bit_cnt + '1';
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end if;
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if (bit_cnt="1110" and clkdiv_cnt = "1111") then
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state <= stop;
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sck_o <= '0';
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spi_o <= '1';
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end if;
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when stop =>
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state <= idle;
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sck_o <= '0';
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spi_o <= '1';
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clkdiv_cnt <= (others=>'0');
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bit_cnt <= (others=>'0');
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full <= '0';
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when others =>
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state <= idle;
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end case;
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end if;
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end if;
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end process;
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end b;
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其中out_reg 一直是0，在idle状态赋不上值，大家看是怎么回事
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