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新手刚学ALLEGRO16.2要搞个大的工程现在ORCAD中进行DRC检查时出现了1000多个错误如下:WARNING: [DRC0004] Possible pin type conflict C616,2 Bidirectional Connected to Power5 @9 I% K$ p- Z
DESIGN, 11 FB MEMORY DECAP (7.10, 3.70) 5 g' H) w3 K* ^' Y' L8 p3 m. X
WARNING: [DRC0004] Possible pin type conflict C839,2 Bidirectional Connected to Power
' G6 b! u H5 h: N+ z# G9 { DESIGN, 11 FB MEMORY DECAP (7.50, 10.40) 1 M3 \. ^* c1 U8 n; z
WARNING: [DRC0004] Possible pin type conflict C613,2 Bidirectional Connected to Power2 `/ W! v* x+ ^% n
DESIGN, 11 FB MEMORY DECAP (7.50, 6.60)
2 d& [- m+ ?6 x: ?, s( cWARNING: [DRC0004] Possible pin type conflict C50,2 Bidirectional Connected to Power
, g* ~, j6 i7 n3 D DESIGN, 11 FB MEMORY DECAP (7.50, 2.80) 7 Y4 J3 K( U6 @8 x
WARNING: [DRC0004] Possible pin type conflict C804,2 Bidirectional Connected to Power! s" E& ]' F7 L3 u2 J
DESIGN, 11 FB MEMORY DECAP (7.70, 11.30) " C* @$ [1 o' k8 _
WARNING: [DRC0004] Possible pin type conflict C597,2 Bidirectional Connected to Power
u3 ^! G0 F, J; X. f DESIGN, 11 FB MEMORY DECAP (7.70, 7.50)
; z4 O% C! Z$ S2 _5 |( c( C: h$ WChecking for Unconnected Nets5 p; P) l- y$ `: M
WARNING: [DRC0007] Net has no driving source SNN_FBA_RFU_2
/ F& Y. I' Q- J( o+ \0 J$ C DESIGN, 05 FBA Partition Memory 1 0f 2 (17.20, 4.90)
5 `) d6 ~- i* q1 `WARNING: [DRC0007] Net has no driving source SNN_FBA_RFU_1
1 M8 i6 v5 f, Y3 ^1 G& R+ d DESIGN, 05 FBA Partition Memory 1 0f 2 (17.20, 4.80)
0 l9 f& L6 m3 S' ~: |WARNING: [DRC0007] Net has no driving source SNN_FBA_RFU6$ @. V F. |% ]6 I l
WARNING: [DRC0006] Net has fewer than two connections SNN_GPU_PD<5>
+ u% [, n. v; E$ I; D# X* O* z8 l DESIGN, 21 PWR and GND Signals (18.80, 9.80)
. C$ L3 R" S1 m" T: EWARNING: [DRC0006] Net has fewer than two connections SNN_GPU_NC<2>' x* @& N3 M1 A: F
DESIGN, 21 PWR and GND Signals (9.30, 4.60)
: o( o1 y: ?5 N, I6 E/ U2 mERROR: [DRC0027] Other parts in this package have different values or PCB footprints. /G1Q( B3 W0 g% |: x) b3 l
DESIGN, 21 PWR and GND Signals (6.40, 4.00)
( U- L6 Z+ A4 _! h! R ~7 {2 f# _ERROR: [DRC0027] Other parts in this package have different values or PCB footprints. /G1T
6 I( L6 ?! B; c9 r DESIGN, 22 NVVDD Decoupling (2.60, 2.00)
) _: V& b& \; y: r# t4 z6 I2 fDRC0004]这个错误最多了(这个好像说是管脚类型冲突什么来的)$ q" n( K2 j* |( b s% U; B
导制无法导出网络表, e! g+ Z3 G1 l: z. H3 c2 P
请各位高手帮忙指点% @1 i! C& w0 {* d' {, M
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