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本帖最后由 drjiachen 于 2010-11-16 22:52 编辑
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6 V: B: P" ~4 D/ ePower Integrity Analysis and Management for Integrated Circuits (Prentice Hall Modern Semiconductor Design Series' Sub Series: PH Signal Integrity Library) (Hardcover)Raj Nair (Author), Donald Bennett (Author)
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Hardcover: 360 pages Publisher: Prentice Hall; 1 edition (May 3, 2010) Language: English ISBN-10: 0137011229 ISBN-13: 978-0137011223
: g3 X1 q. P9 ^: r0 rNew Techniques and Tools for Ensuring On-Chip Power Integrity—Down to Nanoscale
7 L# b7 \" y1 M" u& L1 NAs chips continue to scale, power integrity issues are introducing unexpected project complexity and cost. In this book, two leading industry innovators thoroughly discuss the power integrity challenges that engineers face in designing at nanoscale levels, introduce new analysis and management techniques for addressing these issues, and provide breakthrough tools for hands-on problem-solving. , Z0 Z, z6 @2 z
Raj Nair and Dr. Donald Bennett first provide a complete foundational understanding of power integrity, including ULSI issues, practical aspects of power delivery, and the benefits of a total power integrity approach to optimizing chip physical designs. They introduce advanced power distribution network modeling, design, and analysis techniques that highlight abstraction and physics-based analysis, while also incorporating traditional circuit- and field-solver based approaches. They also present advanced techniques for floorplanning and power integrity management, and help designers anticipate emerging challenges associated with increased integration.: n& [9 N) u$ I: E
The authors
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* x3 R( \ L0 l; V0 t- Systematically explore power integrity implications, analysis, and management for integrated circuits
- Present practical examples and industry best practices for a broad spectrum of chip design applications
- Discuss distributed and high-bandwidth voltage regulation, differential power path design, and the significance of on-chip inductance to power integrity
- Introduce Anasim RLCSim.exe, a powerful new tool for power integrity aware floor planning (downloadable for free at anasim.com/category/software)
- Review both traditional and advanced modeling techniques for integrated circuit power integrity analysis, and introduce continuum modeling
- Explore chip, package and board interactions for power integrity and EMI, and bring together industry best practices and examples
- Introduce advanced concepts for power integrity management, including non-linear capacitance devices, impedance modulation, and active noise regulation
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4 b" r7 H* ~; W& u2 W+ D% j* a' `Power Integrity Analysis and Management for Integrated Circuits’ coverage of both fundamentals and advanced techniques will make it indispensable to all engineers responsible for signal integrity, power integrity, hardware, or system design—especially those working at the nanoscale level.
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! o/ \, y- X' C I- jAbout the AuthorRaj Nair is a veteran of the electronics industry and academia with more than 20 years of engineering and research experience, holding over 40 patents in VLSI Design and general electronics. He has engaged in power management and power integrity investigations at the electronic system, circuits, and device levels in his efforts, of which the most notable are his work at Intel Corporation, where he researched and conceived of integrated CMOS voltage regulation for power integrity management for nanoscale microprocessors. Raj founded ComLSI Inc. and Anasim Corp., where he worked on developing advanced, patented techniques and tools for ULSI power integrity analysis and management. / S' c4 J/ G. T. g. b0 p0 J
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Dr. Donald Bennett, a device physicist and veteran of the semiconductor industry, co-founded Anasim Corp. with Raj Nair. Donald is also the inventor of the patent-pending "Effective Current Density" method facilitating high levels of abstraction and physics based simulations for integrated circuit and system power integrity analysis. Prior to Anasim, he founded QuantumDA Inc., developing and deploying RLCSim, a grid simulation software employing the ECD method.
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Table of ContentsPreface
' P' v0 Y5 t2 L& \7 e7 R: I0 {9 ?0 jChapter 1: Power, Delivering Power, and Integrity
$ g6 q: A. |2 A1 z9 U1.1 Electromotive Force (EMF)% [3 _& s/ M$ w9 }; z- v z
1.2 Electrical Power0 J, G6 W, `# j5 F7 I( W
1.3 Power Delivery) _- Z. u- o, b E8 p
1.4 Power Integrity (PI)8 i4 R! m s1 M$ z% c+ A
1.5 Exercises% t, {! a9 v6 B7 d; _
References
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Chapter 2: Ultra Large Scale Integration and Power Challenges
9 k5 |0 a8 Y* g2 v+ Y" @2.1 Exponential integration and semiconductor scaling, Q9 j9 @+ ^: N3 ^$ z* a. t' ?! c
2.2 Power and energy consumption
3 u# q0 E4 b7 | i f! y- U2.3 Power, heat, and power integrity challenges
" W9 _* e5 S. {! _0 W2.4 Exercises6 [0 B4 `8 V1 e6 b
References+ |4 w$ z( v$ g/ o) l
a; w. @. S5 Q$ ?" E; U cChapter 3: IC Power Integrity and Optimal Power Delivery
6 k! J6 z( @7 d& h) S2 L3.1 Power transfer and efficiency, B4 k: V' y' q+ Z# n9 I$ L! e
3.2 Optimal IC power delivery: on-chip inductance and grid design/ R g) Q6 `* d$ o
3.3 Power grid cost factor tradeoff analysis and design% Y: i9 x/ A9 z* p1 {
3.4 Exercises
- B& ?* K5 U0 g& t! s( B7 sReferences
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Chapter 4: Early Power Integrity Analysis and Abstraction
7 S% }# z7 ]( z& O' m; w1 n4.1 Process, voltage, and temperature: design verification space+ J; T, x }1 Y; m$ M* C0 @; R
4.2 Back-end and front-end PI analysis
8 T2 h; |4 r* h& U% Y' j s8 |4.3 Simulation environment for models of high abstraction levels, F# V1 z. J/ n4 x
4.4 Abstraction and PI analysis examples& k5 U' | h! ^
4.5 Summary and enhancements, Q; {3 f( W( L
4.6 Exercises+ P- W2 `! V5 q! \ [" Q
References+ e4 q" |4 t1 I6 b6 \
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Chapter 5: Power Integrity and EMI/EMC Integration1 \( y8 q! D, o) f& a5 L ?, a
5.1 Introduction
# u, a" g t* I$ c5.2 Analysis of Noise Generation and Propagation through Power Distribution Network
1 `/ b- W. _/ p/ b+ Q5.3 Modeling of decoupling capacitors for noise mitigation in a PDN
$ z# ^, X# E' J, `1 g5.4 Current design methodology of power delivery networks
! @- b: G0 d. f7 r; v5.5 Modeling methodologies+ c H" z) O$ D. F) o
5.6 Numerical methods
\% Z% J+ ^( b p5.7 Power/Signal delivery analysis tools and limitations. g C( x) A3 f
5.8 Power integrity aware electromagnetic interference (EMI) analysis
4 a, J% N& a& u5.9 Strengths and limitations of exiting early EMI methodologies
3 G! Z; |3 g2 ^, h* [7 ~5.10 Early power integrity-aware EMI modeling and analysis flow4 n1 a& z. ~# N. o2 k( G6 Z8 w
5.11 SI, PI, and EMI summary J, ~) A3 U* ~8 h& J
5.12 Exercises/ y; I; Q8 {& `, j7 |; L
References
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Chapter 6: Power Distribution Modeling and Integrity Analysis
1 g) f5 C: Y5 Z! J/ f0 m6.1 Introduction
1 t. l/ h8 ^2 O9 ~6.2 Modeling of a power distribution grid$ R7 U- e1 {& ^4 e
6.3 Numerical analysis of a power distribution model. {4 R$ o- j/ ?2 k1 G0 P' B
6.4 Differential and common-mode noise
" p5 N5 K( m* ^9 I6.5 Verification and error analysis% F1 ?) x, }( h
6.6 Modeling of on-chip bus switching current3 [* V% `3 ?8 J# \9 ?7 G
6.7 Verification of bus model
! H, F9 f% Z2 t) X1 q6.8 Bus skewing to reduce power distribution noise
5 F9 n+ d; ~( L; I6.9 Case study: Reduction of power distribution noise& t, y7 k4 a; n1 o4 q$ n, t7 U+ m
6.10 Exercises
( _( ?) k5 P( n v9 u$ z6.11 Appendix: Coefficients for equation (6-37)
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' d3 z+ ^+ `( v" R* T* RChapter 7: Effective Current Density and Continuum Models
. C) A% c4 A8 W7.1 Circuit and model simplification h$ o# y4 r* M* I
7.2 Definition of effective current density# R" }9 d; k0 z# Z, o z# d, y
7.3 Effective current density and virtual currents
% T6 B& n, e# l p4 B0 D7.4 Symmetry in networs containing conductors, insulators, and other components
7 L# e- R5 N/ D' w1 E7.5 A continuum model employing ECD
+ T- n% j5 Y+ t8 \$ Y7.6 Practical application of a continuum-based simulator to IC floor planning
$ L" D! m0 b& l, |+ c! P7.7 Continuum models compared to SPICE models
3 T$ W( U8 m$ u* m7.8 Model enhancement for nanoscale CMOS integrated circuits
$ ]4 a+ Y1 Z' `7 Z1 U+ W7.9 Exercises7 G E/ q' C- d2 ^( g5 Q
References
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Chapter 8: Power Integrity Aware Floor Planning and Design3 ^; f, q# N, S3 Q
8.1 Design for Power Integrity: Nanometer era considerations
- y9 c" c( T1 d' B; R8.2 Design for power integrity: Techniques( e ?1 b8 g& U) D/ G9 E
8.3 Power management and power integrity
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Chapter 9: Power Integrity Management in Chips and Systems
( [/ I! ]" m4 T d0 ]" h9.1 Chip-level PI management
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9 S" {! }2 X' O9.3 Exercises5 e6 l3 L+ o, N
References. Q9 n* y, m# B. T
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Chapter 10: Integration Trends, Challenges, and Power/Integrity Management
; b# L; X* K( s5 o10.1 Chip-level integration1 s" j) }# S5 d
10.2 Package-level integration
, }$ f' {+ N& a# T' v10.3 Integration trend for power integrity management components
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发表于 2010-11-16 22:50
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