标题: Hotfix_SPB16.30.008_README_CCR（更新说明） [打印本页] 作者: T45524093 时间: 2010-6-3 12:25 标题: Hotfix_SPB16.30.008_README_CCR（更新说明） DATE: 05-14-2010 HOTFIX VERSION: 008 . b6 ]' A/ e: p8 {( s+ t5 P- T=================================================================================================================================== 2 |' ]) @, N3 D+ {7 xCCRID PRODUCT PRODUCTLEVEL2 TITLE, u, k$ e! A- x4 d+ B1 e
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697699 CONCEPT_HDL HDLDIRECT SCM Verilog output contains the line 揹efparam <instance number>.SIZE4 R: N' x+ j- N! Y6 e
734169 ALLEGRO_EDITOR PLACEMENT Wildcard asterisk character giving "illegal char(s) in refdes entry." error in quickplace. + [3 \3 P- ^3 A% ]' K738970 SIG_INTEGRITY GEOMETRY_EXTRACT power bus issue with SSN simulation when device is on bottom, R2 i5 t4 {- v n/ B' P
744762 CONCEPT_HDL OTHER Connection dot sizes do not match on printout vs. screen & s9 F& u& }& y3 s) l! A750371 MODEL_INTEGRIT GUI Model name in physical view cann't match the model in right workspace . }& G9 q# S1 S. w; P' X757024 CAPTURE STABILITY Capture crashes while exporting to EDIF$ }' j& Z3 v4 @
759094 CONSTRAINT_MGR INTERACTIV One member of a diff pair will show Analysis Failed when analyzing the design., s/ T) B7 z. P6 o) ~
760178 ALLEGRO_EDITOR EXTRACT Crash Allegro when executing extracta command for big size design(size of .brd* ~$ |4 } G* d1 |. A3 H1 L+ c
761391 SIG_EXPLORER OTHER Incorrect rise time1 P% P9 R! y* a$ d; n' s
762402 ALLEGRO_EDITOR MANUFACT When photoplot(RS274X) of MM unit was loaded, shape was broken.5 v, ?( z" H) M( q( m
762783 SIG_EXPLORER INTERACTIV sigxp - coupled tline on stackup layer should show solved impedance ! z# P) Z4 D6 l6 C7 p763150 ALLEGRO_EDITOR OTHER Request - IPC356 output truncate the padstack size to fit into the columns 59-62 and 64-673 ?1 v8 {: U6 n% @! L
763556 SIP_LAYOUT ASSY_RULE_CHECK Assembly Rules Checker is displaying an array of confusing DRC's on a Soldermask shape.4 C2 N0 Z$ C5 P7 n
764399 SPECCTRA ROUTE Manually routed trace in Allegro are ripped OFF after routing in SPECCTRA using Route > Route Editor.8 @, r1 Y; K q, a4 Q
764475 SIG_EXPLORER INTERACTIV topologies from earlier versions cannot be opened in 16.2 on a machine o( ]' d' [4 j9 `
765287 ALLEGRO_EDITOR PAD_EDITOR attempting to open padstack fails with - database has a non-recoverable corruption.+ b7 @0 }$ b! t, X, S" |
766041 ALLEGRO_EDITOR OTHER Auto B/B via generator incorrectly defines some BB vias : X3 s a5 {9 _* ]9 O! |0 Y$ `/ p1 u766153 ALLEGRO_EDITOR SKILL Allegro crashes when trying to extract padstack information * U9 l5 L- G; Z4 t766611 ALLEGRO_EDITOR EDIT_ETCH slide creates DRCs in ARK area. X! r4 S, C( n. [: U
767041 CONCEPT_HDL CORE The tap command failed because the specified tap body CTAP is invalid * e; T0 `$ {, J767146 FLOWS PROJMGR Project manager open last open .cpm in 15.7 version not in 16.3 % e7 {4 S0 E f% M" R767526 FLOWS PROJMGR Project Manager customization does not work 2 z9 |8 k. T7 j# S3 Y* I4 e767671 APD DATABASE Crash creating cline with axlDBCreatePath() on this database.7 b- l1 ^$ }9 \' K# \
767951 ALLEGRO_EDITOR DATABASE color net param file omits nets with bus brackets in the name 7 [, q5 v3 C H7 I; X1 M768168 CONCEPT_HDL CORE Fontsize on instances changes when doing backannotation$ z7 \# m0 s! \6 i
768207 CAPTURE STABILITY Capture crash while editing properties ( c9 Y; \4 e2 A# T0 k# x0 @768734 CAPTURE PROPERTY_EDITOR Properties of title block are not getting editted through spread sheet. ) H$ X. m7 O& P768832 APD DRC_CONSTRAINTS Following Performance Advisor instructions results in much longer DRC check time. / ~$ x2 i( m. J6 W6 U768990 F2B PACKAGERXL RFSIP architect 16.3 85Y Schematic to SiP fails due to softinclude in cds.lib file this problem does not occur on 16.2 4 j, W' B/ G# y0 @769097 SIG_INTEGRITY GEOMETRY_EXTRACT Sip Digital SI-Bus Simulation function will shut down auomatically when it is running7 b. m7 d E; w% O7 _2 e; r8 I
769235 SPIF OTHER need to be able to remove mbs_spif* properties added by mbs2brd 4 l/ c/ K @+ m7 w769326 CONSTRAINT_MGR DATABASE Length by Layer crashing 3 p. Q& T) t' O) m3 w# X/ n1 G5 n769336 ALLEGRO_EDITOR TESTPREP testprep density - returns Unable to add the PROBE_DENSITY subclasses., e }) I$ `% Q" F
769458 ALLEGRO_EDITOR OTHER SMD Jumper has a problem about the connection point when using the Add Jumper4 r: I! g' y9 v) m! n, G" {. l. q! D
769845 ALLEGRO_EDITOR EDIT_ETCH Diffpair routing out affected by line to line spacing rule. - f5 R' B% z' d' R$ }& s769934 SIP_LAYOUT WIREBOND Duplicate Finger Name. , S. g8 d. |0 s6 P% O0 Q" M770006 ALLEGRO_EDITOR OTHER Ratsnest_schedule[Power_AND_Ground] can not show figure without move symbol.! t7 p g; R7 J" ]
770125 ALLEGRO_EDITOR DATABASE PCB SI GXL Via Labels grayed out on formand labels not visible on the canvas & E/ W4 W& V) o' g770212 ALLEGRO_EDITOR DRC_CONSTR Incorrect Etch Turn under SMD pad DRC error on this board; D B' b. K$ S3 M# t: h! a
770230 ALLEGRO_EDITOR ARTWORK Artwork fails to suppress unconnected pads on pins with the net_short property. " h3 l* c: Y- d' o770233 ALLEGRO_EDITOR MANUFACT Fillets are not behaving as intended. L- X/ `) C0 p( I2 w
770442 SCM PACKAGER Error during Export Physical - The subdesign block instances ares not updated with reuse properties , _1 P/ ~; {; i1 y1 _' S770556 CONSTRAINT_MGR ANALYSIS PCB Editor's Constraint Manager not updating custom constraint cell.5 y0 U# y: i7 s, I7 f7 f8 j/ n* A
770861 ALLEGRO_EDITOR PADS_IN PADS translation fails with no error message 3 D( g2 @8 g0 p/ I2 }770872 SIG_INTEGRITY OTHER Opening Orcad PCB Editor for this board takes Performance License as well # }; E8 z6 Y, }& ^2 q771117 ALLEGRO_EDITOR DRC_CONSTR Allegro PCB Editor crashes on Update DRC-16.3/hotfix0069 f/ P. J( V# U2 G
771181 ALLEGRO_EDITOR PLACEMENT Component deleted completely from board file after we Mirror and rotate them while moving them. 4 N+ x- b, H- C$ k4 m, X771256 ALLEGRO_EDITOR DRC_CONSTR Update DRC consumes system memory and crashes allegro after approx 30 minutes 1 d n1 M9 j% H* o+ a a771423 ALLEGRO_EDITOR SHAPE Shapes - Update to Smooth - Low on available memory please exit the program.' |: p! b, u" s* u0 g5 W+ l
771456 ALLEGRO_EDITOR EDIT_ETCH Allegro 16.3 crashes when using arrow keys) p6 P$ s/ a$ y# T* e5 w0 a R
771719 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license. ( m- m2 S1 @' K9 z9 M771765 ALLEGRO_EDITOR PADS_IN PADS translation fails to translate symbol) ^! x0 F* @9 i' h% z* J! H
771766 ALLEGRO_EDITOR DRC_CONSTR Moving certain components takes a long time on this board database.. v9 g6 k3 X) E3 { U
771815 SIP_LAYOUT IO_PLANNER SiP OA co-design flow does not allow a save to the .sip file after modifications in IOP 1 m& W% N* l. Y3 \! d1 F773072 SIP_LAYOUT ASSY_RULE_CHECK wire to wire same profile/ N3 A! n2 \) f G( ~
773126 CONSTRAINT_MGR UI_FORMS Constraint Manager "Value Filtering" for Topology Schedule is missing TEMPLATE and "UserDefined" ( V% o! G+ x+ f' e- j3 [773179 ALLEGRO_EDITOR PAD_EDITOR pad_designer crashed when attemting to delete internal name layer. - s% i9 s, n9 J$ f q" V% l% g773229 ALLEGRO_EDITOR OTHER Netrev never end importing netlist generated from Capture CIS2 J) V1 l n! k# K# C1 @1 T* p
773329 ALLEGRO_EDITOR MANUFACT Allegro closes when performing a Linear dimensioning and then selecting the undo icon., J) \* ?% x; X h2 ^/ D
773483 ALLEGRO_EDITOR MODULES place module problem : @0 Z9 _1 L6 l774036 ALLEGRO_EDITOR INTERACTIV Rats not shown after move->mirror command 1 l, q! d9 R) J j774170 ALLEGRO_EDITOR DATABASE DBDOCTOR fixes Error but it reappears and Artwork fails; [ Y) V; U/ p
774602 SCM OTHER ASA crash while working with hierarchy 7 S% l* G( w" e774643 CONCEPT_HDL CORE DEHDL crash on edit of attributes& d' q/ u! a( ?3 U
775201 ALLEGRO_EDITOR SKILL Color palette can only be changed one time using skill commands, R9 P/ q: ^7 U% R/ f) R% z0 H$ r
775815 SIP_LAYOUT WIREBOND Unused wire profile once purged using wire profile editor are still available in CM and Color dialog/ A5 p2 }0 ]" ~1 n$ ]7 z
775826 SIP_LAYOUT WIREBOND Cannot change the Wire Profiles on the wirebonds in this design ! ?; q3 Q) v% f775842 SIP_LAYOUT WIZARDS Die text in wizard is changing DIE location when origin set in DIE text file is other than 0, 0 $ M& q. M) p% G7 M, H+ tDATE: 04-23-2010 HOTFIX VERSION: 007, @0 K. D% f* ]
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=================================================================================================================================== ) H% d1 a# Q( S0 H721859 ALLEGRO_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why? + P" k: p- l: d9 U740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp' z/ Y3 Z( m2 X
744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools# W" }% W; {: ^; F* x
747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0. 7 Y& L- _- L( d) Q* L M747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash. 3 t7 t9 I4 q5 r ]3 E/ b751372 CAPTURE OTHER Copy / Paste Issue in capture 16.3 ' L! R& t9 z( w$ S757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit. ' C* @& x$ w% D0 a0 ^5 _0 h8 B4 T759906 CIS PART_MANAGER Property copy from one to several parts doesn't work9 U( N p: D5 [# Z9 ~
760154 PSPICE NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result+ R1 \4 ]. P; x! E
761177 CIS OTHER Error Message - Memory exhausted1 |! C& I% M' j4 q( T
762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location.- H2 p5 q$ g. u- ?
763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.3 l& w- `1 b3 D1 a+ E
763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created. # V/ s% _+ w* G# ~; J' G763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager? 3 s# j0 d' \; R9 G) ]764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.3 0 p- C. ]* q6 l6 }- j" f3 ^+ @( n764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle.+ S' X- w- F% K0 X" N7 `) H
764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad, @7 `5 ~6 |% e+ d! k Q g+ @9 f
764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.3 Z* H: E2 s/ w2 c
765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro6 b3 c2 H; f1 R1 W
765319 APD DRC_CONSTRAINTS Identical Constraints in Performance Advisor question % X2 m2 `/ c+ Y7 ?; R# o765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape. . B4 i' U, g3 x766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle1 B( `: R9 S& w: K
766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design ; |# R7 ~( H: O4 W' }& {& }766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.3! x, r* p/ ~( k7 o( C$ V: D' Z- I
766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit . e+ p! S+ J* |" b. [, x; R767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version.; Q6 ~9 c: B, L
767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step.2 x1 b4 n: G, H7 G9 e9 @
767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs. . u2 u# t. R3 u- ?+ v( |767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly # {5 \9 L6 H9 w' h( n; q768822 ALLEGRO_EDITOR SKILL axlSetParam return value is divided by 10 to the power of the design accuracy. . {. T/ r' C- `& n9 s$ _1 c8 @769150 CIS PART_MANAGER Update All part Status on a group changes 揇o Not Stuff?status to 揝tuffed?in V61.3_ISR_5. ?8 p3 A( k J6 X% {' HDATE: 04-09-2010 HOTFIX VERSION: 0060 y/ l4 Y9 `* N! O- _
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=================================================================================================================================== - v# D- }$ g: t745241 CONSTRAINT_MGR TECHFILE Importing a tcf file automatically enables On-Line DRC. 7 E* I) F s' [% x2 Y3 x% F2 j752587 ALLEGRO_EDITOR PLACEMENT Uppercase File name(XX.mdd) for Placement replicate update on Linux. 3 [' p. _ X! N4 ^753626 CONCEPT_HDL CORE newgenasym error while saving the hierarchical block symbol o' `6 b$ @" z1 b7 P) @% S, r
753894 CAPTURE OTHER Case sensitive version control S/W1 f% z7 W& L! K3 i w3 V \
754487 RF_PCB OTHER Various asymmetrical clearance problems uncovered - calculation issues?$ Y$ \, E8 t: R2 R
758272 CONSTRAINT_MGR UI_FORMS Entering values on the Min/Max Propagation Delays worksheet hangs the application. & p7 [, m; S# k' Z' h* r758911 PSPICE PROBE Pspice crashes while exporting probe data using our sample project$ s! N& v3 \$ Y3 `! [" x v
759871 CAPTURE PROPERTY_EDITOR Save option in Right Mouse Click on property editor of nets doesn't saves all the changes. . A6 ^3 m- D3 r( L( d& c+ b# O759890 SPECCTRA ROUTE Specctra autorouter ignoring prerouted nets ) P+ B" c. t$ Y" `& C760067 ALLEGRO_EDITOR SHAPE Dynamic Shape not getting filled on board with odd angle placement and routing % c( N& M8 a, F760284 CONCEPT_HDL CORE Update Sheet Variables turns of the grid & L7 |% x1 F! b760480 MODEL_INTEGRIT OTHER Message open clipboard failed when trying to open the rename/reorder dialog in Model Integrity- P: F3 T: N% `* H; z& o9 [
760667 ALLEGRO_EDITOR PADS_IN The pads_in.exe translate incorrect drill shape from PADS 2005 ascii database. 8 u. e0 m) A7 E% D* {+ O760741 ALLEGRO_EDITOR MENTOR mbs2brd does not work in 16.3 but works in 16.2- P' ~' e& c1 a5 R1 A7 ]) Q6 E
760810 CONSTRAINT_MGR INTERACTIV Deleting Region Deletes NCCs2 A( c) c( W- Q& f" ?
761114 PSPICE PROBE Refresh issue in Display > Cursor window5 \/ u( S i7 B) Z% ^ Q: z
761180 ALLEGRO_EDITOR DRC_CONSTR Via_at_smd not working for custom shaped padstacks. / a$ D1 |) |+ {9 O/ ?+ c& J# ^0 u- X761305 SPIF OTHER Allegro crash when seleting any of the Route - PCB Router - submenu items. ( C. O% i+ W/ W: _0 p. b761376 ALLEGRO_EDITOR PAD_EDITOR Wizard_Template_Path is not considered for symbol template look-up ?5 L$ g7 V8 F1 J! k2 m. f9 ?4 r# z
761416 ALLEGRO_EDITOR DATABASE Allegro crash on chaning the subclass for group of clines 5 w0 K; o% Q3 u$ n8 d* E1 S& z761492 ALLEGRO_EDITOR SKILL about axlTransformObject function/ |6 R- B& I" O0 B2 g6 x: j
761518 F2B PACKAGERXL about mismatch library path between cds.lib and actual- `# u. a* S6 b4 Z! H4 O0 s
761737 ALLEGRO_EDITOR OTHER Running Dbdoctor after executing Skill is giving symbol fit error for the .dra file & c- ~5 G5 f2 {7 o6 S+ [! k762155 ALLEGRO_EDITOR SYMBOL Updating a symbol changes the netname of the cline resulting in drcs. 4 g& k& K$ n$ X1 R6 s, v762181 ALLEGRO_EDITOR OTHER Allegro netrev crashes for long device name in PST* files 8 C! e( v9 h% W) d5 P762316 ALLEGRO_EDITOR MANUFACT Allegro disappears on Adding dimensions for the symbol file+ L) X" l& n" D9 X7 j$ k' J
762792 ALLEGRO_EDITOR PADS_IN PADS_IN fails for SPB 16.3( ]' \- ]& P. i& N: Y% l
763108 ALLEGRO_EDITOR SHAPE Z-copy shape create an error like VOID boundary may not cross itself 5 Q4 A# |/ q: f763134 SIG_INTEGRITY SIMULATION Bit 7 of a simulation is out of sync with rest of bus. It should be the same for all bus values.% {% L0 ]' k7 g9 W
763149 CIS GEN_BOM CIS BOM in V16.3 is not correct if database has Quantity field and its value is 0.2 k; J, r9 a- l8 B7 z" j
763296 ALLEGRO_EDITOR REFRESH The error was happened while doing the SUM. P# z+ o+ u: a/ }- A% H3 \( f1 e* Q) J8 G
763303 ALLEGRO_EDITOR OTHER SMD Jumper has a problem while using the Add Jumper. @8 B9 [3 F0 x: @# p9 b
763315 ALLEGRO_EDITOR PADS_IN pads_in got error message WARNING ERROR(SPMHDB-205) 0 r& | c: s2 o: y, U/ O- w7 L763354 ALLEGRO_EDITOR PADS_IN Auto suppress redundant shape while using pads_in translator; V4 M/ M& |" U( C0 ]1 M, o; d2 V0 l8 B
763428 ALLEGRO_EDITOR PADS_IN enhance pads_in.exe translate spacing and physical rule into Allegro. 3 R& B0 B; ~9 W( g3 E763446 ALLEGRO_EDITOR REPORTS missing fillet is reporting pad without drill6 S6 J( F$ l, x9 J. Y
763448 ALLEGRO_EDITOR DRC_CONSTR Performance advisor shows Cset as unused nets when it is assigned to Diff pairs or xnets. 3 a. `3 }8 c0 @2 |763586 ALLEGRO_EDITOR DATABASE Allegro rounds off the value after decimal in CM . c$ b9 Q: i) G) |3 X( x764077 CONCEPT_HDL CHECKPLUS The output predicate in the Graphical environment is not always returning the pin object for an output pin. % l6 R- _. K \6 A, W, b( K, B/ HDATE: 03-26-2010 HOTFIX VERSION: 005 8 }6 Q1 }' f1 |# m {5 j===================================================================================================================================. Y+ {. C7 y0 p$ E0 c
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599819 SIP_LAYOUT 3D_VIEWER display soldermask by default in the 3d viewer * [" x3 C$ l0 i7 a* C735992 CONCEPT_HDL CORE Create Test Schematic does not use the correct package type- Y g' N8 ^1 h9 _7 q
743787 SIG_EXPLORER OTHER 16.3 SigXP crash if sigxp.run created by previous version exist.3 W9 k9 J# {# R0 c, ]& }
746320 CAPTURE NETLIST_ALLEGRO Remove Semi-colon from invalid pin-name check during netlisting 5 a0 o# m. q& ?' b: U3 d746444 ALLEGRO_EDITOR OTHER show element fails to display info on a via if it is in a module. 8 R7 G, {/ ]6 G8 ~( I% L1 v746726 SIG_INTEGRITY SIGWAVE Save As and Open Dialogs open in last saved directory % u+ U# R6 M8 D' t750080 CAPTURE NETLIST_ALLEGRO Improve error message ERROR(SPCODD-390), l; m+ f V3 R: @. |0 y+ V6 O
750606 SIP_LAYOUT ASSY_RULE_CHECK Wire to BF same profile check! R9 w9 _3 K/ o- A% A- P* i
751492 CAPTURE FPGA Option to swap the pin-numbers rather than their locations in the Schematic after back-annotation" C( o; |2 T( A. ~) T
753834 CIS LINK_DATABASE_PA unable to link multiple database part + m5 `. x4 q* W4 Z7 |1 K0 d1 S4 f: L$ E753990 F2B PACKAGERXL Delay in opening the subdesign tab in the Export Physical setup in SPB 16.35 m( T, ~, _& ]- \
754328 LAYOUT TRANSLATORS L2A gives error Subclass name TOP not valid Allegro subcls with s029 hotfix! M5 I* {. v2 z4 P7 {6 f" c d
754434 CONSTRAINT_MGR OTHER allegro crashes when deleting matched group & }- J3 i3 O) k4 d+ q7 [0 [755111 ALLEGRO_EDITOR INTERACTIV "ALT_SYMBOLS_HARD TRUE" property does not work when I mirrored symbol using move command in 16.3.; K9 c* r7 U" F/ f, U
756131 PSPICE SIMULATOR Capture crashes while re-running simulation7 u) ^5 h; w- @- O/ s3 p
756148 PSPICE PROBE Zoom Area in Probe Window does not work for digital signal in SPB163" q7 J+ V2 k& T. T- b) E
756169 SIG_EXPLORER OTHER Signal Explorer crashing due to sigsimcntl.dat, t; N4 O$ E' E7 e7 ~1 O$ ^- N5 E: q& }
756176 PSPICE PROBE Trace color is wrongly interpreted in PSpice probe window.( Y6 v; O& d1 A" d3 _
756224 SIG_INTEGRITY SIMULATION Simulation aborts reporting that VIA models have changed1 l8 N2 k; L6 i- Z! n% E2 U# H. Z E
756281 ALLEGRO_EDITOR OTHER Why *.sav file cannot be recovered from PCB Editor utilities? , {% r# p* }/ a5 W; e. u756673 SIP_LAYOUT ASSY_RULE_CHECK Running ADRC Metal to metal checks causes false X-D DRCs, cannot clear them and trying crashes the tool0 F- l. f6 x) P. [- J
756918 ALLEGRO_EDITOR OTHER Allegro angular dimensions working incorrect in 16.3 + V2 g1 i3 J. ^756932 ALLEGRO_EDITOR CREATE_SYM Create symbol fails with error duplicate pin number: a. `. Y$ X, k: u) e- b
756976 ALLEGRO_EDITOR SKILL axlChangeWidth always return nil in Allegro version 16.3( g) G2 ^7 j9 e% @' A
757000 PSPICE NETLISTER Incorrect Hierarchical Format Netlist created # f4 U( B! J# ^' m757406 APD OTHER Implement Segment over void features in APD L& q& q: u& ]2 E% A) J4 Q' E+ A
757624 SIG_EXPLORER OTHER Sigxp runtime error when simulation is run and exit without saving the topology # k8 S8 @) L6 W' }% t4 _$ _757820 ALLEGRO_EDITOR SHAPE Shape does not void to hole if there is no pad & w1 V' m; w/ g+ p# f' F P) K758009 ALLEGRO_EDITOR OTHER Export > Library (MECH_SYM) adds a new subclass NCROUTE_PATH, data moved from one subclass to another. 2 Q" M* g8 P# T' g7 N758022 CAPTURE DRC Capture crash while running DRC with 揜un Physical Rules?checkbox.& H- c8 i, [! K/ B$ Q* f2 |
758190 ALLEGRO_EDITOR PAD_EDITOR PCB Editor crashing on pin move in this design 8 { Y) X: P G8 s. p' [758374 F2B DESIGNVARI Problem with Mechanical part in Variant Editor / l x$ I, P2 W+ I' Q; d! j( {758471 SIG_INTEGRITY OTHER Differential impedance does not change on changing the etch effect values.; z! T q2 u b
758490 CIS CRYSTAL_REPORTS Different crystal report output in 16.3 than from 16.2* K! v- t& ^5 c2 k( R t
758498 CAPTURE NETLISTS PCB Editor netlister hangs: a& S8 `7 b" ~9 _$ F/ E
758584 APD SHAPE Shape not voiding all elements " T; v1 l% W8 J+ P0 J2 N758886 ALLEGRO_EDITOR REPORTS Total number of nets is wrong into Testprep Report o. g0 W- u; ^6 N3 A6 Z: Z
759146 ALLEGRO_EDITOR SKILL The title is not displayed in the form by the version. / i4 n2 [9 ~* N: q i I759339 ALLEGRO_EDITOR ARTWORK artwork output fails by SPB16.x. 3 {/ d) f9 |! ]5 I2 ~7 V759591 ALLEGRO_EDITOR SKILL axlSetParam fails and does not round the value as indicated by the warning message 5 R# H i$ b. g6 D. O759816 CONSTRAINT_MGR OTHER Allegro Hangs when double click on a Bus in CM 0 C( j. b% p% K3 A& ~6 [3 q4 i3 m759947 APD OTHER Need an a way to convert Lines into Clines. l' X; B* G* [& P
760353 ALLEGRO_EDITOR MANUFACT Allegro crashes and creates a .sav file on running the silkscreen command from Manufacture > Silkscreen ! o# y! G% a# p6 L760432 ALLEGRO_EDITOR PARTITION Unable to remove fixed property after partition import/ m3 [* A( H! S# A; M' C. j
760638 ALLEGRO_EDITOR PADS_IN pads_in translator can not handle " PINPAIRGROUP ". 7 p! W( z: @; F ~6 Z6 D: @760734 ALLEGRO_EDITOR SHAPE Different therma contacts on rotated partsl( Y- X! g8 k% w
761436 CAPTURE NETLIST_ALLEGRO SPCODD-53 Error when creating netlist with PACK_SHORT 5 L6 O) I+ s7 c! bDATE: 03-12-2010 HOTFIX VERSION: 004 % W$ D9 @( j Y=================================================================================================================================== 1 o8 p1 W" ^1 c7 i) @+ qCCRID PRODUCT PRODUCTLEVEL2 TITLE) ]$ j) w B% j
=================================================================================================================================== 5 z0 y3 @3 E! J& P689495 ALLEGRO_EDITOR DATABASE corrupt database 2 w6 n5 ^# }2 J" M/ o" U725944 SIG_INTEGRITY GEOMETRY_EXTRACT xtalk make allegro freeze and never give hands 0 A: r) m1 o" W l7 W4 ]& W( `732604 SIP_LAYOUT SHAPE Shape Issue - added shape will not clear around other elements. . i. j. g$ V" g740106 PSPICE NETLISTER The "Enable PSpice AA Support for Legacy" option does not give the Desired Monte Carlo results 5 b, i6 @# O; l744259 SCM UI Signal order reversed when a Vectored Signal name is renamed in reverse 4 e8 ?7 @& m+ G4 F/ ^" b1 |9 s745554 SIG_INTEGRITY GEOMETRY_EXTRACT Time to get Xtalk simulation result in 16.2 is lower than acceptable by comparing the time in 15.7 / {$ T9 s. {$ N745595 RF_PCB FE_IFF_IMPORT import iff RF_PCB give an empty block5 g9 S; R6 h2 ?7 D: K
747133 CAPTURE STABILITY ERROR [DSM0006] Unable to save 7 V( z9 N, V. k! m747679 CAPTURE STABILITY Trying to Save the Design in 16.2 format gives DSM0006 Error and crashes Capture3 k$ ^0 R; a6 C8 H. h+ y1 p
750460 CIS FOOTPRINT_VIEW 3D footprint viewer doesn't shows the footprints2 p2 F2 M+ y, f8 x
750777 SIG_INTEGRITY OTHER Trace impedance showing wrong 4 f7 P2 B" [7 {8 |. j a9 A& P751424 ALLEGRO_EDITOR DRC_CONSTR Unexpacted DRC for Shape to Route Keepout ! f' ?& W# P7 F* K. }0 z751897 SIP_LAYOUT SPECCTRA_IF Radial Router crashing SiP tool3 B! d; B/ o: L( t- O
752029 SCM OTHER Cross probing not working between SCM and Allegro Editor in Linux Environment ( |! p5 [: [* J8 t) s7 A752450 APD PADSTACK_EDITOR APD crashes when selecting a User Definable Mask Layers. * Y ~$ `* ?! E1 _1 E, j* n752581 PSPICE PROBE Pspice probe window crash }9 M& U% m! `3 h
752709 ALLEGRO_EDITOR PLOTTING Sheet content doesnot plots title block1 X& }/ q+ Y, r! ]" S) ~# D
752908 ALLEGRO_EDITOR INTERFACES Output from Export > DXF shows one instance of a via on the wrong layer# e/ {' \* R( L: v' Q) Y
753226 ALLEGRO_EDITOR OTHER File > Change Editor doesn't shows the default Product Options ' H4 S- E4 }5 D/ [- k4 ]/ @* e753622 ALLEGRO_EDITOR GRAPHICS Enahnce capture image command to default the save as location to working dir ( o, A/ c2 c2 ]! y0 }4 f753773 APD WIREBOND Requesting the option to set the diameter of the default WB_TACKPOINT power ring pad. 3 p% v0 [) o% H7 q753778 APD IMPORT_DATA Import NA2 displays the design momentarily and then crashes 0 Z, P) p4 S: t9 p/ H* J: F753866 SIG_INTEGRITY OTHER about Select by Polygon after move command / M' j4 w9 Q, V3 |# {753958 CAPTURE OTHER Capture V16.3 is extremely slow while edting schematics of design placed on network drive via VPN. 7 Y; |# a5 \7 \7 y1 g754050 ALLEGRO_EDITOR UI_FORMS Why show element window disappears when scriptmode is set invisible% T1 b' y1 r( V, x! |+ e; C0 J
754143 SIP_LAYOUT OTHER SiP Package Design Integrity - running Extra Cline segments generates report without Layer number " K: ^8 n2 G5 b754327 ALLEGRO_EDITOR OTHER Rename Sub Class is not working as desired. 2 E; h$ C( S* x Q9 N754364 ALLEGRO_EDITOR PLACEMENT Crash when applying placement replication0 S9 V+ @& O6 f. P4 g
754462 ALLEGRO_EDITOR SHAPE Allegro circular dynamic shape fails to fill. ?, E8 r$ c" o+ m5 k1 C' E$ Y
754819 ALLEGRO_EDITOR OTHER Create details shows wrong graphics for filled curves # I4 e h2 ]3 T2 A755176 ALLEGRO_EDITOR PADS_IN Pads translation succeeds in v16.2 but fails in v16.3 on this ASCII file2 l) V; J1 V3 L% `4 q% y- Q
755256 ALLEGRO_EDITOR OTHER Attached script is crashing the designs in v16.3) F" |" D7 i! }: }3 B' R x
755610 CONCEPT_HDL CREFER Cref hyper links does not work for signals where number "0" used to define the zone for page border 8 B7 ^5 W7 Q" j+ B( U4 Q+ h0 h7 `1 w755787 ALLEGRO_EDITOR EDIT_ETCH crash using resize_respace_dp command - g+ }& p# y9 B/ \2 w5 L/ r755881 ALLEGRO_EDITOR DATABASE Swap component crashes application) z$ }' H( b6 v% r( |6 e/ P2 l$ t
756092 CAPTURE PROPERTY_EDITOR property editor flickers and loops on value edits M- ?" }3 y7 o) }( x- Z
DATE: 02-23-2010 HOTFIX VERSION: 0035 W* k4 w1 B; y; `
===================================================================================================================================" a& Z" [, l$ A6 q/ |; I, J9 \4 H3 T
CCRID PRODUCT PRODUCTLEVEL2 TITLE% d1 }; R% E2 ~3 U3 M0 y
===================================================================================================================================, E- J( A+ V& u6 x
263504 CONCEPT_HDL CHECKPLUS Checkplus fails to run if crefrpt exists in the design & h/ S# o( X! K9 j; M4 f. b- V) m726836 ALLEGRO_EDITOR SKILL axlGeo2Str() and axlGeoEqual() return different results v6 g5 m( C+ q+ _; a
730820 SIP_LAYOUT PADSTACK_EDITOR Changing the Via diameter will cause the SiP tool to crash ; y! \4 U2 q- `% j735193 CAPTURE FONTS Pin_names and Pin_numbers get convertred into darkened blocks in 慫oom to all?view in V16.2. # }4 i$ P2 h2 d/ B% L+ Y! ^7 I737307 SIG_INTEGRITY GEOMETRY_EXTRACT differential pair extraction to sigxp fails to extract coupled sparam via models - p }, [2 B( H) `5 B740936 ALLEGRO_EDITOR SYMBOL Confusing error message during Create Symbol3 K7 e* |; J2 W5 V
744191 ALLEGRO_EDITOR EDIT_ETCH Arc routing enhancement/ L# Y) T+ s( J! U8 u! i: P
744497 ALLEGRO_EDITOR INTERACTIV PCB Editor Crashes with Data Customization Feature9 G& M! g% F* C) ^2 ?
746572 ALLEGRO_EDITOR DATABASE Reoccuring error in attribute pointer to attribute invalid on dra. 9 k+ T( f* _' ~' Z746978 SIG_INTEGRITY SIGWAVE 2 licenses were used for SigXP and SigWave.+ C# ]$ _; q4 C; J/ q2 @) E2 p
747219 SIP_LAYOUT SHAPE Dynamic Filleting not working with odd angles * c+ e) J& V- x9 s0 F1 z747593 ALLEGRO_EDITOR PADS_IN Some RULE_SETS cause the PADS translation to fail. _" D4 S5 J% O9 [. M
747746 ALLEGRO_EDITOR OTHER Request for more detail in downrev.log file& `1 w" k+ o* T& k. v9 b
748033 GRE IFP_INTERACTIVE Enhancement in GRE where Show Element on Bundleshould show the total number of nets that are part of the bundle& n: | c" i3 h. O+ A5 v
748333 ALLEGRO_EDITOR OTHER place by schematic page number not showing pages correctly% E) ^7 i. n: }4 I" A; O
748375 ALLEGRO_EDITOR MANUFACT gloss - line smoothing causes crash0 f8 E Q, f9 _4 Q' P
748818 ALLEGRO_EDITOR DRC_CONSTR Undesired DRCs shown in allegro 16.3 while moving component and the same are removed by update DRC0 t* T8 d: I( j8 a
748865 CONSTRAINT_MGR OTHER Allegro 16.3 slow to move component with CM open % y9 v+ r/ t1 I% W. P+ ]! y749009 APD WIREBOND a part of function of the finger alinement doesn't work 2 X0 J+ I/ H4 S' }' b749162 SIG_EXPLORER INTERACTIV Unable to proceed after RMB > Preference > Cancel& q% B) T( f4 m2 [
749307 ALLEGRO_EDITOR MENTOR mbs2brd fails with error VIF_Allegro_Write0 Y- `+ G) k, |1 N6 W
749435 CIS DESIGN_VARIANT Cannot create variant part in 16.34 S0 _" T* ~3 A- ~, w
749854 APD PADSTACK_EDITOR The value of user-defined mask layer is not retained in the design.) o7 [1 w# t% W5 h3 S. i4 C
749891 ALLEGRO_EDITOR PARTITION Unable to delete existing partitions % h W) M& N N% w% P749949 SIG_EXPLORER EXTRACTTOP A Topology extraction fails using APD and SiP series with the latest hotfix(SPB16.30.001). 3 x; s# _7 ?. J: N0 h7 J! o750008 CAPTURE NETLIST_ALLEGRO Netlist different in SPB 16.3 and after installing SPB 16.3 hotfix 1 : h/ \4 A, z8 T, ~4 O750591 ALLEGRO_EDITOR DATABASE Analyze diff pair object fails to display uncopled lenght values. : M& O1 Z4 w3 D6 ^, s) Y750888 SPECCTRA ROUTE specctra is crashing while routing " @& n( i+ p8 P" f# S# A751204 F2B DESIGNVARI Design difference crashes while reading funcview ! m1 q3 \, q: \' I6 J751398 ALLEGRO_EDITOR OTHER Allegro Crash when Edit is selected in Setup > Outline > Room outline 1 J' d8 _: f) h& N3 b/ ~751578 ALLEGRO_EDITOR PADS_IN pads_in hangs while conversion" M) ~+ j( O9 \( B6 h. c/ u0 U, ?( F
DATE: 02-09-2010 HOTFIX VERSION: 002 6 q! }# B: U# C4 ?$ `$ L===================================================================================================================================- h$ ?9 j7 B+ E. x2 d
CCRID PRODUCT PRODUCTLEVEL2 TITLE( V! N9 y7 J8 l
===================================================================================================================================! `$ C" V) s9 w: x2 q8 h
527012 SIG_INTEGRITY IRDROP Severe Memory leak in IRDrop* R) p" s9 U0 k7 ?2 g3 E
623678 PCB_LIBRARIAN CORE PDV freezes when changing grid 0 k" W; H: H3 |0 X* ?672592 ALLEGRO_EDITOR SHAPE Shape does not void correctly untill a clearance oversize value is added0 Y" s' |0 E" s+ G# `, ~4 g' p
688062 PCB_LIBRARIAN CORE PDV Strange characters appear when copying text into Bus Arrows ( Text symbols) 8 \; c1 j) I# a8 Y/ `# \710170 SIG_INTEGRITY IRDROP Run IR Drop even if all components on the net are not placed. ) v8 }# J9 U6 G2 n710174 SIG_INTEGRITY IRDROP Audit function for IR Drop. 8 b5 x0 {3 f: i6 }2 w726833 PSPICE DEHDL Modify the methodology for migrating 15.7 and 16.2 users of ConceptPSpice 3 C3 R9 q; N8 L730717 SCM UI Unable to delete a zero connection signal in SLP which has a pull-up! Q, N# M% |5 v& j7 M
731017 ALLEGRO_EDITOR DRC_CONSTR DRC's show out of date when artwork is run3 J4 E8 S1 k+ d, V4 N' [
732145 CONCEPT_HDL OTHER Incorrectly generated VHDL netlist( h8 c. U) y3 U5 f
740123 ALLEGRO_EDITOR GRAPHICS Capture Image command fillin missing from jrl and script files % W# S4 T; f4 W0 n, b740278 ALLEGRO_EDITOR OTHER Jumper fucntion for Single Side PCB Design: e) J7 q" \: Z3 w; Y9 N% A- p
740656 ALLEGRO_EDITOR GRAPHICS Can we place custdatatips.cdt file on a site level for SPB16.3 9 u1 h; o. _; u! B- x* Y$ N! c741222 CONCEPT_HDL CORE Replace command (in Windows mode) causes crash0 P) g% P# s, Z5 F% b7 F) G$ h5 H
742389 ALLEGRO_EDITOR EDIT_ETCH Change or add message when using Countour route + \0 F" |4 S$ M4 B743275 APD DATABASE With DRC enabled, this design seg faults in axldbid.c (solaris only). DRC update takes orders of magnitude longer on sun 2 \! P" g# H( y0 O. @743623 F2B PACKAGERXL Pxl error when using pack_ignore on reuse blocks+ J7 R/ M0 A2 |+ t
744348 F2B BOM PART_NAME column getting word wrapped inspite of sufficient space in the HTML BOM report. ! O+ u' x1 E9 u% \: | Z3 x745062 CONSTRAINT_MGR OTHER import techfile does not add new layers in cross section7 {) a, o. \! Q: C
745148 ALLEGRO_EDITOR GRAPHICS Allegro ptf driven HEIGHT value not pushed into 3D Viewer 8 Q6 \& R+ Y+ j745301 ALLEGRO_EDITOR DATABASE Allegro 16.3 crsh on moving component$ W1 S- i4 B8 i+ }
745518 ALLEGRO_EDITOR DRC_CONSTR DRCs not shown when "Enable Antipads as Route keepout is checked in"+ L$ w; o& S. u D3 b& G
745745 SIP_LAYOUT WIZARDS Die Text In changing the pin names on duplicates( A! o/ F/ l6 H ^3 s
745785 CONSTRAINT_MGR UI_FORMS Unnecessary window opens when the cell in PCSet By layer worksheet was clicked.( b' t# D& @! R" F7 ] T7 u( w4 O) i
746002 CONCEPT_HDL CREFER Could not find pc.db in the root design9 \/ L8 A5 l m5 n: \! F' f
746010 CONSTRAINT_MGR SCHEM_FTB Updating the brd file using the "Import Changes Only" option overwrites the modified constraints in, @* t& b" N9 Z2 ]$ T
746080 CONSTRAINT_MGR OTHER Click Constraint Manager filter icons crash software . p9 N8 u) D" j9 y746137 APD IMPORT_DATA Import > NA2 not transalating certain layers and padstack sizes ! e; L5 S: n* H746370 ALLEGRO_EDITOR GRAPHICS Setting infinite_cursor_bug_nt variable flips mouse movement on flip design! c; G9 e _* g' M
746519 CONCEPT_HDL CHECKPLUS CheckPlus the if statement is not seeing the True condition or the output predicate is not returning the True condition. 4 ^2 ^. h, q `) v746546 PCB_LIBRARIAN VERIFICATION con2con choosing incorrect PART_NAME in PTF File during verification. Y) ?1 Q. U0 i2 V4 }" W4 R; J3 M
746865 CONCEPT_HDL CORE Tool generated pspice net names in core concept design cause short with copy all./ C4 ?- T. F& K4 s- s
747636 SIP_RF OTHER RFSIP Layout RF Module Export chips & connectivity is not writing die attach method to chips file2 p6 i, T& F6 b3 j. ~# d4 E& ]
DATE: 01-31-2010 HOTFIX VERSION: 0019 ^$ A* g* w* X
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CCRID PRODUCT PRODUCTLEVEL2 TITLE2 a/ \5 p% i' @) C0 ~) @
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491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute . R1 |8 }6 c6 i0 @/ [496910 CAPTURE NETLIST_ALLEGRO Inconsistent netlist creation % I% ?/ ^4 f# N8 A558783 PSPICE NETLISTER Why do Models with "awb*" prefix need wirte permissions to "*.ind" files? ) u9 K! s2 I, C e) [643241 CAPTURE SCHEMATIC_EDITOR OrCAD crashed while replacing cache Z2 c0 n' H7 |, Q) j654292 ALLEGRO_EDITOR DATABASE Propagation Delay constraint behaves differently between 16.01 and 16.2' G! O+ e/ d7 T& {
662829 CONCEPT_HDL GLOBALCHANGE Global Update should honor property visibility settings in ppt_optionset ; C+ j# P3 j' D8 x/ g1 Y+ j0 I672718 SIP_LAYOUT EXPORT_DATA "Export>Symbol Spreadsheet" should export a .cvf not a .txt; o; E8 s# e# S, ^5 [" h
676233 CAPTURE NETLIST_ALLEGRO Cross probing stops working if design name has dots/ o3 w0 \6 J+ H
678739 CONCEPT_HDL CONSTRAINT_MGR Manually added targets in matchgroups lost when reopen CM, R6 e% Q' ?7 O# h
690618 F2B BOM Write protected template.bom fails to write callouts & X, Q4 Y7 a5 ~0 r' a3 o7 P0 K5 e700246 CIS LINK_DATABASE_PA Need option to update symbol always when linking part in CIS, n& p# c- [! q) `4 i; x% Z! w
705393 CONCEPT_HDL CORE ConceptHDL crashes while switching to another hierarchy level under File > Plot Preview.8 @ @8 c. e) ]9 {0 j
708634 ALLEGRO_EDITOR SHAPE Shapes getting incorrectly displayed in 16.2* F. L/ u5 e3 {: B2 K5 N# c
708950 CONCEPT_HDL CORE Tool crashes while trying to change the text on the schematic using a text editor. 9 }8 n( P. B- T |* a; s709823 ALLEGRO_EDITOR OTHER Arcs not converted properly when upgrading symbols # v8 N& t M& M4 D713964 F2B PACKAGERXL Net property Probe_Number is getting changed during the packaging run ! I/ Z I$ D2 \$ a718119 F2B BOM Exclude the callout file name from the template.bom file7 s0 U& d5 i: Q
718496 SIG_INTEGRITY SIGWAVE Frequency at smith chart. S/ C" N0 T5 J- ^- t* t b1 f) ?
721422 CONCEPT_HDL CHECKPLUS Checkplus fails if "\\" character is used in the parameter list & Y) @8 S3 l7 `2 g721788 SCM OTHER SCM unresponsive while closing out a Block without Saving 2 a8 ^; E# r v# V0 b" c6 c% T721801 CONCEPT_HDL CORE Save As crashes DE HDL if an existing page is selected in the design5 H2 Y# h' L7 e2 Y& d0 S7 J/ m# K
722653 F2B PACKAGERXL Packaging does not complete& Z- C* o) R. |& v2 q* s
725285 CONCEPT_HDL CORE nconcepthdl does not work same as concepthdl for same script.5 g3 G0 j: @( p8 l
725719 CONCEPT_HDL CORE wire pettern of Publish PDF ( z% |& {9 |5 j. Y% F. |727062 CONCEPT_HDL CREFER Custom properties not visible for TOC symbol in schref_1 view" m7 K. V- ]7 v0 r$ V
727194 CAPTURE CORRUPT_DESIGN Random Capture crash1 ]0 @( u. p1 s) M4 ]: B& m* g4 l$ O+ v
727704 SCM PACKAGER ASA to PCB getting out of sync' q8 |' b" s5 i! q
728066 CAPTURE NETLIST_ALLEGRO Allegro PCB Edtior net cannot be generated if PACK_SHORT is used: E) B2 c! Z, L& o9 }# }
729214 CONCEPT_HDL CORE SHOW_PNN_SIGNAME directive used with Windows Mode gives crash . ^% j; h+ X8 |) X# s3 J9 Q' P730295 SIG_INTEGRITY OTHER Filled rectangle shapes not extracted properly/ Z, d9 Q2 B' ]+ t" O5 n$ q
731183 CIS QUERY_DATABASE CIS Query fails with ODBC Error for query (Price contains 29) 7 w+ C) O3 r- I6 u+ W" M4 a732073 SIP_LAYOUT DXF_IF DXF_OUT generate an incorrect shape( H: q# x' S5 a! S9 _5 w. H
732138 CONCEPT_HDL CORE Cannot change SI model assignments $ \' }# j5 F; {732216 ADW DBEDITOR dbeditor crashes doing copy-as-new into lib folder that has partially completed chips.prt file. L4 l8 m% Y4 f1 M$ \
732249 SIG_INTEGRITY SIMULATION Probe sim with custom stimulus cause segmentation fault. Linux only. ' D5 J$ m9 E5 n% C( {$ X$ u732847 ALLEGRO_EDITOR DRC_CONSTR Manual Void uses Shape to Pin constraint to void Holes! c: Y% l* H% \( h% l( A! g
733261 FLOWS PROJMGR Project manager does not work with the Restricted User in client server environment. y: \" V* A4 G
733773 CONCEPT_HDL OTHER Syntax issues in DEHDL + \" O5 I Z& G" \734260 APD COLOR Why subclasses still remain visible even after global visibility is turned off.: O8 @9 v9 r& I1 O4 H
734419 CONCEPT_HDL CORE Concept crashes in windows mode when netname is deleted on schematics generated by ASA# c' H" m3 P- ?
734555 CONSTRAINT_MGR SCHEM_FTB Import Logic does not overwrite the Constraints" b" M( |7 L. S$ [5 R# ]8 |
735290 CONCEPT_HDL OTHER Concept's PDF Publisher has issues." K) V1 y) {. E
735892 CONCEPT_HDL CORE "Component Modify" changes visiblilty of Key properties , Q1 U' @4 E& R1 J+ V2 @' `7 n735977 ALLEGRO_EDITOR MENTOR Mentor to Allegro translation fails without any error message$ _) d+ D7 {) ~, F: J7 Z
736071 CONCEPT_HDL CORE Property visibility is not retained on the schematic instance when we modify the component on sch.1 C6 M a1 [- X- f m- G2 _/ e0 v
736165 SIP_LAYOUT SCHEMATIC_FTB about error message of "schematic to layout"( R% r0 e V7 V
736167 CONCEPT_HDL CORE HDL crashes when I select BGA symbol in Component Browser& B. h8 J3 X7 u( {
736911 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge0 m1 y" x! o7 Q' k& |
738035 ALLEGRO_EDITOR OTHER Measure function has different result between 15.7 and 16.2 version. % k% L" G! C4 \1 T+ B# c; K' J6 k738129 CONSTRAINT_MGR UI_FORMS Need Diffpair Constraints option in Analysis Modes Electrical Options with Performance license& K0 o% v/ R; P5 [8 j$ `
738276 ALLEGRO_EDITOR PLACEMENT No feedback in console window when placing unfound components in Allgero 16.3+ w# k; w7 x. \
738366 ALLEGRO_EDITOR GRAPHICS 3d viewer not showing some connectors with mutliple place bounds correctly" E3 L7 ^4 X% t1 S" o
738454 SIG_INTEGRITY FIELD_SOLVERS EMS2D extracts incorrect CPW to Trace spacing6 `3 @2 T0 f0 I9 R
738578 ALLEGRO_EDITOR OTHER scriptmode +w doesnot work on Linux* K# j2 ?' p) }7 M' n( A
738869 ALLEGRO_EDITOR OTHER Error msg when cds.lib contains missing SOFTINCLUDE 4 G) O4 b# ~, \3 K: {$ @! S739116 EMI SIMULATION At EMI simulation on SigXP an extra Sigwave form is launched.0 K3 d2 B9 x1 {
739225 ALLEGRO_EDITOR GRAPHICS Ability to lock the 'Hide Pallette' option ; [; X, i" W* O! f" X& o+ F B739599 ALLEGRO_EDITOR DRC_CONSTR drc_errchk indic 2 |6 P9 K& e3 ]4 R* e' t# `8 p739628 ALLEGRO_EDITOR SYMBOL Opening a symbol file is crashing allegro.& a1 n# F0 P4 _# B
739653 ALLEGRO_EDITOR SHAPE Shape created in 15.X .dra changes geometry when uprev'd to 16.X+ }6 l0 {! V" w4 }- v" {) j
739661 ALLEGRO_EDITOR OTHER Export netlist creates incorrect via_list syntax. ) v* X# P" U" b V1 t( A) o" d739872 ALLEGRO_EDITOR SKILL Crash while performing axlExtractToFile in 16.3 4 ^& D7 o" F- m B739934 SIG_INTEGRITY OTHER specctraquest crash on changing signal model ; b, y. f& {' \6 B% F# q+ b: T739937 MODEL_INTEGRIT PARSE zero valued estimated parasitics in ibis models/ H0 i9 e9 Z4 J' J
739942 ALLEGRO_EDITOR SHAPE zcopy xhatch shape creates oversize copy. X. l" ~% q5 b1 _
740133 ALLEGRO_EDITOR DRC_CONSTR Same net DRC Update from Analysis Modes runs forever. Q& B( B7 z0 y8 t740281 ALLEGRO_EDITOR OTHER Jumper components where were placed in PCB disappeared 7 j8 i Y; k3 N1 h% g/ t/ f740309 SIP_LAYOUT DIE_EDITOR Moving a die pad in DIE EDITOR on G69A_U1 causes the die pads to rotate 90 degrees from the design. . w# {7 b1 V* G$ _7 o9 h3 |4 ~740399 ALLEGRO_EDITOR COLOR Cannot automatically load custom color palette in 16.2 0 o' v6 c/ m6 x; d# j7 j741210 ALLEGRO_EDITOR DATABASE Edit >Move; spin creates 'connect record not found' message % m7 f7 G9 t- E- ?3 m741307 ALLEGRO_EDITOR PADS_IN Shapes on some layers is not getting translated from PADS into Allegro 4 l F. R% _1 B E2 D+ L3 z0 U G( h741313 ALLEGRO_EDITOR DRC_CONSTR Add connect slow in 16.3, g0 i o! C. s
741778 ALLEGRO_EDITOR COLOR Color pallete in 16.3 is not expanding when maximize dialog# _/ g! N1 A. ~0 Q/ m
741910 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd 9 F4 B* o* }' d% s741939 ALLEGRO_EDITOR PADS_IN PADS to Allegro Translation fails or hangs.! G, M' u- j: ]$ s) s
741980 ALLEGRO_EDITOR PARTITION Import of parition does not import etch or vias.5 L* c% H- r% W* i# H. N
742676 ALLEGRO_EDITOR SKILL Tpoint cannot be moved by using skill.0 ^8 N! i! n; f* X( W
743161 ALLEGRO_EDITOR SCHEM_FTB Netrev crashing when importing netlist into board file.( \ ~9 \3 `1 V t6 F. [
743235 ALLEGRO_EDITOR PLACEMENT Allegro crashes when unmatching comp in placement replicate. ! F) g( [. x7 A* _, z) B3 m% ?" l" K743243 CONSTRAINT_MGR TECHFILE Closing CM destroys tcf values when they are set to locked using fObjectNOTReadOnly / U, ?! a' r" H! b% g0 v743301 SIP_LAYOUT DIE_EDITOR Edit die command creates two extra die pads 7 P- ~9 }3 [3 W0 M743316 CONSTRAINT_MGR DATABASE With Allegro 16.3 Constraint manager takes to long to update ! p! P4 N7 X2 `- K( G, ]2 }& l743553 CONSTRAINT_MGR OTHER Net disappears if we cancel the line width edits in CM作者: 黑月 时间: 2010-6-3 13:13 作者: zhouhua_8 时间: 2010-6-7 23:12 作者: blueguyhk 时间: 2010-6-8 09:05
noted & thanks作者: afeionline 时间: 2010-6-23 09:44
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