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Orcad Capture CIS 导网表问题,求助!

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发表于 2009-8-22 23:28 | 只看该作者 回帖奖励 |正序浏览 |阅读模式

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本帖最后由 whb3103536 于 2009-8-22 23:30 编辑
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) h8 C7 W9 C$ v: G" O& \) h/ k" ~各位我在用Orcad Capture CIS 16.2 导网表时遇到一些难题!如下:- _0 O7 T) c5 b4 u

9 O7 O: ]% U) c' x********************************************************************************% i$ N& i' U  V2 V4 {7 j
*2 U" z. S) F& [8 x
* Netlisting the design 6 L! T" j% D6 L. X8 u: E
*
3 Q' E# s" ]4 ~5 m' L0 }********************************************************************************3 s( k; M7 R2 f5 Q9 X
Design Name:/ n% \" n5 z. J
f:\work\g-plus\g120\sch\g120_allegro.dsn( a7 b( U% R1 @6 e3 z- _
Netlist Directory:& T! e' t7 s  j) @1 A
F:\PROJECTS\CADENCE\G120\NETLIST7 o2 ]: q* F$ E
Configuration File:
! d7 i9 T% |, v3 B: Y  eC:\Cadence\SPB_16.2\tools\capture\allegro.cfg

* z1 \0 [; A: O, h8 f3 tSpawning... "C:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "f:\work\g-plus\g120\sch\g120_allegro.dsn" -n "F:\PROJECTS\CADENCE\G120\NETLIST" -c "C:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
3 u& o* {# f# s+ \- h) i#1 Warning [ALG0016] Part Name "BATTERY-CONNECTOR_3_KBC23S3M_R_BATTERY_CONNECTOR" is renamed to "BATTERY-CONNECTOR_3_KBC23S3M_R_".: N% v& Q- s, j
#2 Warning [ALG0016] Part Name "SCHA1A0101_1_T-CARD-PUSH-PUSH_AC0200-030" is renamed to "SCHA1A0101_1_T-CARD-PUSH-PUSH_A"." {" z  l7 \9 Z4 O- x0 I
#3 Warning [ALG0016] Part Name "CONN FLEX 5_FPCKEY_5PIN_FPC_KEY_CON" is renamed to "CONN FLEX 5_FPCKEY_5PIN_FPC_KEY".- j6 D5 ]' e9 I0 s( T* M7 R
#4 Warning [ALG0016] Part Name "SIM_CONNECTOR_3_AC0100-063_AC0100-063" is renamed to "SIM_CONNECTOR_3_AC0100-063_AC01".. S% O1 @5 D8 L8 d- j. G+ E9 d
#5 Warning [ALG0016] Part Name "CSTN_0.4'_C15DDS29_CMC1P4236-E_CMC1P4236-E" is renamed to "CSTN_0.4__C15DDS29_CMC1P4236-E_".
9 Y4 _5 O5 K3 T6 k/ N* r7 c2 c#6 Warning [ALG0016] Part Name "GL826 LQFP46_3_QFN46_GL896-LQFN46_4.5X6.5X0.66MM" is renamed to "GL826 LQFP46_3_QFN46_GL896-LQFN".# Y+ ]0 {/ [5 ^5 z
#7 Warning [ALG0016] Part Name "TOSHIBA_TV00578002_0_FLASH_256_128_S71PL_N" is renamed to "TOSHIBA_TV00578002_0_FLASH_256_".
3 q2 Y. h+ f( o3 `8 X8 |! A, Q#8 Warning [ALG0016] Part Name "FAR_F5KA_897M50_D4DC_0_SAW_5P_FAR_F5KA_897M50_D4DC" is renamed to "FAR_F5KA_897M50_D4DC_0_SAW_5P_F".( t' E0 t$ ]2 x6 H. ?) r# m% [
#9 Warning3 D; U' A6 {7 K
[ALG0016] Part Name "TCVCXO_1_CRYSTAL_3225_SQ3D02600B2JBA" is renamed to "TCVCXO_1_CRYSTAL_3225_SQ3D02600".
% N/ N, c5 F) Y% g- P1 r: f#10 Warning [ALG0016] Part Name "BT_SAW_0_LFB182G455G9A293_LFB182G45SG9A293" is renamed to "BT_SAW_0_LFB182G455G9A293_LFB18".
% t$ T/ Z) a) ~" m' Q0 _0 K1 m: P; P#11 Warning [ALG0016] Part Name "SGM2022-EYN6/TR_SOT23-6_SGM2022-EYN6/TR" is renamed to "SGM2022-EYN6/TR_SOT23-6_SGM2022".
" ^0 D, S. ~$ E1 s7 ^8 P#12 Warning [ALG0016] Part Name "SDFMM1N12CA2T_4_MT6188_MT6188(MTK)" is renamed to "SDFMM1N12CA2T_4_MT6188_MT6188(M".
. K9 n3 `* L8 O' t6 O$ _- M#13 Warning [ALG0016] Part Name "CONN RCPT 14/SM_3_USB_12PIN_MUB01-AK22110" is renamed to "CONN RCPT 14/SM_3_USB_12PIN_MUB".; t- E) {) _, j& y
#14 Warning [ALG0016] Part Name "XTAL_3PIN_CARYSTAL_32K_32.768KHZ" is renamed to "XTAL_3PIN_CARYSTAL_32K_32.768KH".
4 Y% k7 U6 h2 s. a! N! [#15 Warning [ALG0016] Part Name "4PIN_XTAL_CRYSTAL_3225_27MHZ/10PPM/7M32000035" is renamed to "4PIN_XTAL_CRYSTAL_3225_27MHZ/10".% B0 s8 h8 j' Q9 h+ W4 H% _
#16 Warning [ALG0016] Part Name "BZX84C15/SOT_0_SOD2512_NC/CZRF52C6V2" is renamed to "BZX84C15/SOT_0_SOD2512_NC/CZRF5".
9 @4 ?% l, H3 bScanning netlist files ...
( Y6 I# }* Y( Z4 |* c3 W6 D
Loading... F:\PROJEC
) D7 z* R( {0 x$ g' O: |9 ?. YTS\CADENCE\G120\NETLIST/pstchip.dat
/ O4 M3 `' k/ D5 N8 z: g4 o" i* V#34 WARNING(SPCODD-34): Expected ';' character on line 1078. Check the name and value syntax for invalid characters in the primitive definition before the line number.
, r: b9 p, z* S' o% ]/ P              ERROR(SPCODD-47): File F:/PROJECTS/CADENCE/G120/NETLIST/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again.: |% |6 i; m" N  s* ?7 ~% f
#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schematic and rerun packaging.- D8 ?6 r! m/ N) J: |- ?# i
#17 Error   [ALG0036] Unable to read logical netlist data.

& F" C' {; y8 m- k( N" \Exiting... "C:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "f:\work\g-plus\g120\sch\g120_allegro.dsn" -n "F:\PROJECTS\CADENCE\G120\NETLIST" -c "C:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"% m3 x7 R6 `: E7 u, ~8 }

; S" |% ~% V( e2 W5 Z*** Done ***8 [! S. ?( d' M+ b( ]  F, a+ {9 }' @
" ^! v5 w: n) s$ _- {
比如说:#1Warning [ALG0016]中的错误,我原理图中的Part Name 根本不是 "BATTERYCONNECTOR_3_KBC23S3M_R_BATTERY_CONNECTOR"如图1所示。字符总数根本没有超过32个,不知道这个Warning是什么意思!7 o0 u& E- j: x! A8 Z- L% ]' D
2 T+ O4 H7 W7 i6 P
其中网表也还有一些其他的错误!请各位帮忙解决一下!
& r! E6 W) K+ I" }
" l% j8 k6 A% ~1 d" N谢谢!

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发表于 2013-3-17 22:07 | 只看该作者
楼主 问下你的问题解决了吗?我遇到了和你一样的问题* [( S% v: o; f1 {( p3 N: R/ }
#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the design before packaging.5 q% J: {$ K# p# A& C; g
咋么解决?

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3#
发表于 2009-8-24 22:48 | 只看该作者
关于那个警告问题,你可以不用关心,它是Orcad在转网表时的命名规则问题,命名时不只是原理图中的元件名,它还包括了封装的名称以及Value值,超过31个字符后,系统会自动截取31个字符,这不影响结果,可以不用关心

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 楼主| 发表于 2009-8-23 09:35 | 只看该作者
本帖最后由 whb3103536 于 2009-8-23 14:10 编辑
; I6 H5 E3 P3 t4 J- ^3 F, o2 M+ J5 N$ ~8 Z! q
还有一个问题想请教大家:
, {) e' R3 B4 F: B( J* P8 C4 I" B一般在用Capture CIS 转Allegro网表时大家用telesis.dll文件还是直接转成PCB EDITOR格式呢?哪种格式会好一些?
. P, S4 D( b& K1 v" b& A2 @0 s' y; X4 {
我现在用telesis.dll格式转的话,就没有上面这个网表错误!( _" f' G1 D) a; s& p8 P2 u5 m( O
请知道的朋友说一下!$ O3 M4 V/ P* J  f3 e
谢谢!
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