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本帖最后由 紫菁 于 2017-9-14 16:05 编辑
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转 Hotfix_SPB17.20.015_wint_1of1
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Fixed CCRs: SPB 17.2 HF015( t2 T) G7 [7 U! d
03-16-2017
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# N& {" ` K( d9 m& E9 f( OCCRID Product ProductLevel2 Title" m( K5 Y( b$ r$ R0 O% z% M
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1653366 ALLEGRO_EDITOR INTERFACES Unable to attach step model to symbol
, T2 Y2 ^; e+ P% P1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model
) E. P1 A% H) P7 o. E0 H5 u* V z1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function/ C" U1 ]) H" E' S
1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file8 a: k; _7 w& C
1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting Padstack Editor results in incorrectly scaled forms
2 Z- ]' J( M8 z h1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design
9 Y4 x) q! M/ a8 p4 [1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees
$ J; U- f) A y1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.
6 J4 @; _: U( G1 L. k" ?1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
0 S4 k% w( K8 W& x2 q5 ?8 j$ d1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
) ^& x9 e/ R; z1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
. P3 E# i' z8 O, O1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used# m- F+ D$ o# I# E ^7 B
1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places3 j, Z& D$ k" K s% r( b
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value
* e6 z1 V1 v6 }8 ]1 U+ d1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically" F4 p3 U5 P6 r) i) \: [% Y4 E
1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad/ i- m) p0 b+ v' G7 F0 y5 A9 |: k# d9 g/ N
1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout0 H) x2 J# k6 Y+ o5 F& o9 {
1698697 CONCEPT_HDL COPY_PROJECT Copy project corrupts the .dcf file
* e1 O: t* k% j! G9 J1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084
, i: S# u1 u. d" a* F7 T: c; a1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position$ W6 O1 J4 G$ _' Z2 j' j
1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net) R, t" p! W2 N8 s& U- @
1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
# d- g# ?# [% W2 {$ e1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation
( Y/ B% G+ d4 _" D/ ~$ B( e- _( w( N1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates: y$ J2 p; I2 I' x1 T
1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode$ d9 v% h" r1 h
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转：Hotfix_SPB17.20.014_wint_1of1.exe 链接：http://pan.baidu.com/s/1jHFB2Pg 密码：mxnk
j+ [) o: Y V* ~Fixed CCRs: SPB 17.2 HF014& R* \( U$ I7 ]4 J/ f4 m$ W: }
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CCRID Product ProductLevel2 Title# E% a) y- H3 u8 J
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1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships+ C' I% J* i$ w* F2 P U0 `
1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity+ u( t- F/ Y$ K- [" b2 ?
1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-268
0 _; U3 ?$ L; t* y3 _7 A+ V1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data
* n% R5 u( {' B) ]; d1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data
' E8 ?, Y8 c* ~* p: b4 a3 n1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors
( b' K6 g6 H' s5 `" w9 Y1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.
7 P: T3 |3 M. [# x: u, _' H, M1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted& x) J. T! H9 K, G# R$ h. Z2 I
1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location
9 f" M1 Z1 g0 C: X& I& q- z! y1685995 ALLEGRO_EDITOR SKILL All film sequence numbers are returned as 0 when using the SKILL function axlGetParam
9 F4 @4 U7 g2 l# X( K1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately
' i8 H/ v ~! I5 T. R1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6
, z E" k% Q( a1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one
Y5 [4 E. Z* \3 w" C2 o1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled: g* a) P" S9 i7 y8 {! Q# H
1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved( `! _1 W: q' S. X _
1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components
- w8 r9 I" |0 v+ G7 l' d1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers
7 W3 t) g t/ i* w3 `2 D; h1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase
: g, e& a7 X1 g1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement [) K. u. C2 G- y+ I% M: J2 x
1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message3 }1 G( o2 o! k* M! U" m
1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 0113 d# M$ g! L( y; h1 @
1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2
: w; m: d D% c# _# X7 ?2 e1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
6 k" l& U% N8 H" _1 G1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016
2 s- Z" c2 B+ l8 Z C( N1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design
2 G) h0 a d* j, ]$ } U' L1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors5 g% M1 q; [) v/ T- B
1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters5 o" C% ]. j H R( z
1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP/ Q- e4 B# L7 E7 k
1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'
, N0 D3 R; f% G9 a1705265 INSTALLATION DOWNLOAD_MGR Problem installing OrCAD Library Builder from Download Manager
4 C8 E" Q# x# O. l. F1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script
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Cadence OrCAD and Allegro 17.20.013 Hotfix链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv
' M, m: `7 O: `+ hFixed CCRs in SPB 17.2 HF013
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: N2 w0 @& i s* s% M, G& _CCRID Product ProductLevel2 Title
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1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm O/ ], e0 t& T7 R5 u
1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer
: W9 u) @! k# i8 O r7 N) ~1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
' l" |) W# h- N. l* U+ e3 _$ \1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated$ e: u. z; b+ ]
1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated: a$ H) \* P1 y) S
1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board/ c) W# Q V2 H c$ Z' b2 D, A
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
- t7 k8 G2 m ~4 G8 k' D( K1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol+ K% m; x+ o. T9 E1 H
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
/ Q* _ f7 F7 B0 f/ }1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components
; Y# m: i' _ t F# h1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components
9 V* }% }% }3 p( o5 o1 c1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets" O7 E" ~" W0 L' C0 A' p
1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets& I0 W- O4 e3 |( j- z$ ]% @) H
1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF
6 D4 C1 @1 B( B" b+ `1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement: ]* b4 [8 ]4 w4 G4 ?( K; I
1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.5 @8 l* x$ l5 D
1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file- D, X, Z7 b( b& g1 R2 K
1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.+ Q, }* }4 Q: `8 C# ]. r
1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker/ ^$ z9 z5 D, Z; k! B1 F5 W
1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates
. \* X) [+ D* K l* w1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes
" H7 q" _+ v+ m% _1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.
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发表于 2017-2-26 17:05
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