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SDR新书:Baseband Analog Circuits for Software Defined Radio
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Author:
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VITO GIANNINI
. \) T! y/ E3 }JAN CRANINCKX , q1 x" g4 D: A$ y* @# Y
ANDREA BASCHIROTTO
( h y# |) \% f: dIMEC, Wireless Research, Leuven, Belgium
. L# G8 V6 V) iIMEC, Wireless Research, Leuven, Belgium ( T/ B, Y; y7 \& @: w- J" e: k6 o
University of Salento, Italy# P0 q; {2 z/ L8 x& f$ h3 L9 u
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8 P& w J3 K- K" jContents
/ j7 P* {% L( Q% eDedication v & Q$ c) Q, N; J7 L/ M" B
Preface xi % ~" o; F9 F5 u) M+ l: T
Acknowledgments xv
$ t; N, z6 g* H$ t# S3 {1. 4G MOBILE TERMINALS 1 ) Y; s' \9 ?- `3 c; A
1.1 A Wireless-Centric World 1
* w0 [- c; W9 L' q8 O* V! H8 U7 G1.2 The Driving Forces Towards 4G Systems 3
$ x8 ]7 g9 _" Q$ E1.3 Basic Architecture For a 4G Terminal 6
/ I- }$ j. I1 i) s( @3 l1.4 The Role of Analog Circuits 8
4 j5 z' K5 `! k% B1.5 Energy-Scalable Radio Front End 9
4 N$ u# n* T0 G5 }1.6 Towards Cognitive Radios 11 # ~, W4 H+ @$ V. J
2. SOFTWARE DEFINED RADIO FRONT ENDS 13
# N9 [. n/ c, ]" o% q$ I5 _, o2.1 The Software Radio Architecture 13 5 K4 S( Y3 n% j! L0 D) ~1 m
2.2 Candidate Architectures for SDR Front Ends 16
" j( T: h2 M% M5 }# O! W0 S2.2.1 Heterodyne and digital-IF receivers 17 7 ?& c* p% B& Z6 t% D8 M2 a# _6 @
2.2.2 Zero-IF receivers 19 5 \1 T7 i* e: V0 Q, W4 Z# Z
2.2.3 Digital low-IF receivers 22 : I# O6 v7 s' O
2.2.4 Bandpass sampling receivers 24
, J) L& o% n4 r# i. [. e9 g: A2.2.5 Direct RF sampling receivers 26
; R6 u3 L3 g4 a: K+ `$ @2.3 SDR Front End Implementation 27 ) K U+ w0 P: |# g. d: a
2.3.1 LNA and input matching 29 2 l# E' E5 I3 @+ c: {% |
2.3.2 Frequency synthesizer 30
f0 r6 H! @% F+ e ^" Y2.3.3 Baseband signal processing 31
( [/ W& {0 i; g: |% O- k$ E- w2.3.4 Measurements results 31 8 W- n- [& {' G1 s
2.4 Digital Calibration of Analog Imperfections 33 $ S) x+ o; m+ W, g: @# O5 g
2.4.1 Quadrature imbalance 34 ! L7 ?2 o; K& U6 C' |
2.4.2 DC offset 36
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Contents
' l( ~5 }' H4 u+ }" A# W" x8 \) v2.4.3 Impact of LPF spectral behavior 36
; J# y# j; I7 G4 _" E2.5 Conclusions 37
; ]( v d, t6 v6 h" B3. LINK BUDGET ANALYSIS IN THE SDR ANALOG - j; ~, m; E* J
BASEBAND SECTION 39
) p. O( @' N# Y0 r3.1 Analog Baseband Signal Processing 39 6 `4 X. g9 J; `$ D# t
3.2 Baseband Trade-Offs for Analog to Digital Conversion 40 # ]6 ~& v, @2 W" v6 }
3.2.1 Number of poles for the LPF 41
. o: q. p; g' ]% V% ^0 f; W3.2.2 ADC dynamic range 42 & \( A7 \1 e* r9 l& d' w) d
3.2.3 Baseband power consumption estimation 47
; R' E, Q$ H/ g# t& U; a3.3 Multistandard Analog Baseband Specs 48
; E. ?* f v1 P' P1 x1 I6 C3.4 Multimode Low-Pass Filter 49 % i0 j4 R7 z# r9 u) |
3.4.1 Filter selectivity 50
* P% ?9 J4 Z; f6 [3 K$ h3.4.2 Filter noise and linearity 54
/ p/ o- L! h4 [ i3 L3 H3.4.3 Filter flexibility planning 56
8 K' K/ q9 P' n; |3 f( C3.4.4 Cascade of biquadratic sections 59
* ]4 G& c% ]2 ?" h4 P" I+ k3.5 Automatic Gain Control 62 ! ^$ x" P' f9 t/ \2 J( s
3.6 Conclusions 65
, @/ K4 J7 w+ S3 H2 A4. FLEXIBLE ANALOG BUILDING BLOCKS 67 2 L. F* \2 _" E, a# T3 N
4.1 Challenges in Analog Design for Flexibility 67
# Z- R9 o, R5 N1 V: D2 k4.2 A Modular Design Approach 68
, q; O/ f8 p5 l' M; G; Z2 Z4.3 Flexible Operational Amplifiers 70 $ N# @' V0 @* d9 t6 {& v" O# N# ]
4.3.1 Variable current sources 70
- i( b c' r h# I4.3.2 Arrays of operational amplifiers 71 4 ]$ S+ O; x) d( _
4.4 A Digital-Controlled Current Follower 75
) [5 s6 o2 c: Q; \! K& m4.5 Flexible Passive Components 75
$ w- V9 e' \/ i D! @: ?4.6 Flexible Transconductors 77
. p. e4 {5 N6 `3 p7 N4 \4.7 Flexible Biquadratic Sections 78
) M) P! \$ N2 X3 n' {4.7.1 The Active-Gm-RC biquad 79
* i* W: r# D. L( V! ^4.8 Conclusions 91
* [) _& \6 Z) o4 I3 ]5. IMPLEMENTATIONS OF FLEXIBLE FILTERS FOR SDR % e8 p% \7 A8 P' h, H Y0 j/ K' z/ o
FRONT END 93
/ y( Z5 {7 |8 W5.1 State of the Art for Flexible CT Filters 93
! L7 I/ g* r& R5.2 A Reconfigurable UMTS/WLAN Active-Gm-RC LPF 94
. |# S$ [) Q: M5.2.1 Filter architecture 96 " N* o8 F5 M8 m$ v. _# J- }
5.2.2 Automatic RC calibration scheme 97 , P8 k, O3 s7 e! C
5.2.3 Measurements results 1025 l0 J/ w7 W/ ]
Contents
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5.3 LPF and VGA for SDR Front End 105
. C" k9 ]$ u* @- S5.3.1 LPF and VGA architectures 107 $ \0 C$ Z$ L+ {4 c) @+ `
5.3.2 Prototype measurements 111
& x" y2 k( V9 v! ]: I% T/ I5.4 Conclusions 118
/ A/ L; M) f/ Y) \Acronyms 119 i! O7 U* ]1 Y. u6 z
List of Figures 123 $ H! [, ^0 I* h9 @ Y
List of Tables 129 $ W$ m* V6 M8 d2 p! s; W0 n
References 131 & A1 b T9 _6 N9 |/ n
Index 139) Y% w0 K' C- B! [
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