这段文字如何理解呢？为何会进入亚稳态？

mengzhuhao

这段文字如何理解呢？为何会进入亚稳态？
: T5 K5 P. s2 _6 S& Q* k
/ ^: e% u% M% u0 P. D! A. uIf the asynchronous reset is released at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.

mengzhuhao

The biggest problem with asynchronous resets is that they are asynchronous, both at the
assertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the
( q0 o9 P9 O2 N8 x& g! e' |, uissue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the
+ Q, v# Z% ?0 p% p& }5 Poutput of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.
  I! \8 g0 S3 m5 M. E! tAnother problem that an asynchronous reset can have, depending on its source, is spurious resets
2 l) T) v! G/ b% ]due to noise or glitches on the board or system reset. See section 8.0 for a possible solution to
$ G: y2 u. h" k( treset glitches. If this is a real problem in a system, then one might think that using synchronous
8 V0 s9 O( g$ o  E0 ]resets is the solution. A different but similar problem exists for synchronous resets if these
2 D. Y/ r3 v4 N2 S# O, gspurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is
true of any data input that violates setup requirements).