|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
尝试画个层次原理图，很简单，就几个电阻一连，可是画完了DRC的时候总是报错：
2 R/ o3 I; c: d1 L* d" f1 TChecking Misleading Tap connection
. i6 l/ m p4 a+ ?ERROR [DRC0039] Tap may not be connected with the bus Check Entire net. DD1: SCHEMATIC1, top (3.55, 2.30)5 J, E+ ~7 \3 M0 P+ d d
ERROR [DRC0039] Tap may not be connected with the bus Check Entire net. DD2: SCHEMATIC1, top (3.55, 2.30)
# c# T- B: F. u5 {/ o' Z6 qERROR [DRC0039] Tap may not be connected with the bus Check Entire net. DD3: SCHEMATIC1, top (3.55, 2.30)
M4 U" W1 g/ S# G' m6 PERROR [DRC0039] Tap may not be connected with the bus Check Entire net. DD4: SCHEMATIC1, top (3.55, 2.30)/ c6 T- Z* I) }4 \! f) T: d
hierarchical pin name  D[1..4],
5 x! m) Z7 Z1 Hbus name DD[1..4],
, p6 ?8 I2 x2 u- p) D5 L3 x$ ]net alias 分别为DD1，DD2，DD3，DD4。
; U: a4 T9 k) H* F' c问题出在哪呢？如果把根图上的bus name 去掉，就又报警了，
) H% [( ~1 V. ]9 M8 rCheck Bus width mismatch
4 M6 Z$ Q1 |' o. v; oN06946 has not connected with proper width" |# M/ C% J" ]( l
WARNING [DRC0030] Bus width is not matching with the port Width block1,DD[1..4]: SCHEMATIC1, top (2.45, 2.30)
# \6 h+ e, f! g0 \# ?! a9 _( aN06946 has not connected with proper width
& p5 l7 J1 k/ E/ r3 {6 N& J2 ]3 dWARNING [DRC0030] Bus width is not matching with the port Width block2,DD[1..4]: SCHEMATIC1, top (3.55, 2.30) / l8 V/ T; Q7 \" f; q0 `! L
|
|
/1 
发表于 2011-8-17 17:00
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！