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Hotfix中只需要安装最新的版本即可。' ?% _* K) P9 A7 v! q+ \* K
Hotfix024对以下项目做了修正：, ?9 Q" R4 j, n/ D9 U
DATE: 06-20-2012 HOTFIX VERSION: 024
% c7 e% E2 M6 H, @+ P===================================================================================================================================# D1 x4 G% b4 z6 O+ h2 s
CCRID PRODUCT PRODUCTLEVEL2 TITLE+ a% Q$ z, D% X
===================================================================================================================================1 [4 P9 w1 |' h2 q/ c/ ?, Y7 H2 I
982824 ALLEGRO_EDITOR OTHER Import placement fails with a zero length log file.5 t- n8 U/ G' C9 e6 M/ Y
1006437 SIP_LAYOUT BGA_EDITOR SCM not loading the die if dies refdes and LFnames are changed
) J" L1 s7 W& v, u* K1011040 FSP PROCESS Feature to avoid connectivity between fixed voltage Output and variable voltage Input
1 Y5 x- U% T8 m1 o1012985 ALLEGRO_EDITOR DATABASE Allegro crashes multiple times a day8 M1 ?/ V4 ?2 ]8 E
1013644 ALLEGRO_EDITOR SHAPE Sliding trace with oops creates a duplicate shape islands, i* M7 W# B. v
1014351 ALLEGRO_EDITOR OTHER Whenever we open a file (brd, dra) in PCB Editor with an OrCAD PCB Designer license,we get a warning SPMH0D-34
?2 ~5 p6 ^, r1014893 CONSTRAINT_MGR OTHER With CM open layout is extremely slow and Allegro crashes very frequently9 `; @) h+ I6 U, p4 R& H' m7 F6 F, k
1015210 ALLEGRO_EDITOR DRC_CONSTR Deleting Via from an array casues DRC errors1 i) T3 T- e$ L8 `( i+ V
1016546 CONCEPT_HDL CONSTRAINT_MGR Wrong value of NET_PYSICAL _SPACING_TYPE in Attribute form& l4 Z. A7 T* b) R; N" ~
1016932 RF_PCB DISCRETE_LIBX_2A Incorrect Symbol Pin Numbers after import into ADS
* K: `! ?% \4 U1 q" \2 W1017332 APD VIA_STRUCTURE Refreshing Via Structures results in shorting to power plane.- C- Y$ F7 l, U. @) J( B
1017931 ALLEGRO_EDITOR OTHER IPF import fails with error-IPF error : Illegal pen number: k. H' h5 Y; ?$ o: b M/ ?+ m
1018413 F2B PACKAGERXL Export Physical producing different results depending on how it is launched
! Z Z, H6 m" E1018435 APD OTHER Oblong pads in Sip are not displayed correctly in the Stream_out .sf file.( b( G& I- s: {! n8 a
1018936 ALLEGRO_EDITOR OTHER unexpexted DRC eror: l& M. q/ H8 P+ ^0 ]8 @/ M, W
1018978 ALLEGRO_EDITOR DRC_CONSTR Update DRC changes DRC without any change in design
% d# w5 N. s9 o8 p2 d1019303 CONCEPT_HDL INFRA DEHDL custom outport displays error
7 ~. {- F' g# v6 G: P* j n- S2 i i) g1019913 ALLEGRO_EDITOR DATABASE BUG:Bottom pins are also shown in DXF export/ \# x5 N0 `3 h: f# q2 w: Q
1019955 ALLEGRO_EDITOR SKILL axlRegionCreate and axlRegionAdd do not work in a symbol file.
" S& q6 g0 {* N! k/ n( L. ]1020749 ALLEGRO_EDITOR DATABASE 16.2 Parts not updating when opened in a 16.5 database
" a* Q+ v! \5 Z9 n# N6 J3 [1020780 APD COLOR APD crash on assigning color to net using Color192+ U3 y3 B$ N& D/ _( ~
1021033 CONCEPT_HDL CONSTRAINT_MGR Cleared ecsets in 16.3 reappears as mapping errors without ecset names after uprev to 16.5 |
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发表于 2012-6-23 10:23
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