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大家好，以前用AD6,PADS, 与在用SPB16.2,很不习惯呀。
: B$ I+ p9 D& A0 N- r, X 在做完原理图，DRC检查没有错误后，生成网表时，出现：9 T3 G$ d( l0 x! \+ B) g) K7 A
#248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'. Each section must have at least one non-common pin.
( C1 [* F0 a/ A Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.
5 k l& e9 @; X& W 我检查了原理图SYMBOL和PCB封装，也换另外的PCB封装试了试，错误依旧。
5 D: U/ a S0 i6 } 大家帮我看看，是什么原因呀。+ l6 L. F$ I1 @2 ?2 F" E
我在画原理图时还碰到其它的问题：
3 V% u+ K+ ^8 B) D, |6 R 1：元件编号如电阻电容之后，总自动出现一个A或是B, 如：R120A
8 ?6 V) z7 `: R' f* c4 {! T% ^0 ^$ V 2: 在COPY一个元件到另外一个地方去时，本应每COPY一次编号都自动增加，可现在是每COPY两次，编号才自动增加一次。/ ?( A- I' }' B& N
原理图工程我加在附件里了，大家可以打开F3文件帮我看看。
2 w5 i3 G8 y8 }6 |. F8 G$ r 为方便大家检查，我把生成网有的出错贴在下面了：9 K/ D! e- m" f
********************************************************************************
6 C, P% P3 o- a* S: pDesign Name:
& K* I- ?+ z' r IE:\Hi3515FJ_CADENCE\hi3515fj.dsn
+ w) S# E `5 _0 |+ INetlist Directory:
4 E8 E8 k1 y4 Y6 ]" gE:\HI3515FJ_CADENCE\NETLIST1 P( i( O) t w* j' I
Configuration File:' M: m: U X1 D7 J8 t
D:\Candence\SPB16.2\tools\capture\allegro.cfg
; v# r. w3 G+ u& `Spawning... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"% H, H6 c2 p/ s4 l; X
#1 Warning [ALG0016] Part Name "PHONE JACK-4_0_PHONEJACT_4_PHONE JACK-4" is renamed to "PHONE JACK-4_0_PHONEJACT_4_PHON".
: m/ k8 y: ?/ k/ h#2 Warning [ALG0016] Part Name "SN74CBT16214_0_SOP56-20-250-550_SN74CBT16214C" is renamed to "SN74CBT16214_0_SOP56-20-250-550".7 [$ O, ]* |( v3 I4 |
Scanning netlist files ...' G. y$ D5 r5 K0 n) \
Loading... E:\HI3515FJ_CADENCE\NETLIST/pstchip.dat
7 _) m1 _9 x6 V6 U/ V$ M& V#248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'. Each section must have at least one non-common pin.
2 \, i! C9 n, n3 p Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.0 t/ K6 V$ n5 z# c Y$ ^+ _
ERROR(SPCODD-47): File E:/HI3515FJ_CADENCE/NETLIST/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again." g, _3 Q, H8 F# Q
#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schema
/ g7 ~- s8 r5 r: {& dtic and rerun packaging. F* O- B/ E2 s* r3 ^8 h6 q
#3 Error [ALG0036] Unable to read logical netlist data.( Q0 K7 h/ B" ], i# D3 R) b+ I
Exiting... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"' F! R* B9 B6 }" L1 U$ u2 T
. k# I4 k T7 j: A% @5 A
*** Done *** |
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发表于 2011-6-12 12:00
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