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大家好，以前用AD6,PADS, 与在用SPB16.2,很不习惯呀。
# O3 x! X" [4 S 在做完原理图，DRC检查没有错误后，生成网表时，出现：; ~. o" b( I* V) U' V5 c
#248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'. Each section must have at least one non-common pin.( J4 G) l6 E2 J1 d5 a8 p
Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.1 e: Q3 R4 j( |" u
我检查了原理图SYMBOL和PCB封装，也换另外的PCB封装试了试，错误依旧。1 U' O$ b4 [- P" @2 z; a
大家帮我看看，是什么原因呀。+ ~/ O/ L7 P4 x6 s
我在画原理图时还碰到其它的问题：
1 e' _( Q2 W4 M; q% I 1：元件编号如电阻电容之后，总自动出现一个A或是B, 如：R120A $ ]8 S8 ?- w4 j% G: N! h$ I
2: 在COPY一个元件到另外一个地方去时，本应每COPY一次编号都自动增加，可现在是每COPY两次，编号才自动增加一次。
4 W, c2 Y( W; M% G2 x 原理图工程我加在附件里了，大家可以打开F3文件帮我看看。2 P" K4 d6 B! n7 _) m3 v
为方便大家检查，我把生成网有的出错贴在下面了：* Z- F9 X: U- H: V1 S% C
********************************************************************************
( o/ \* l* k3 pDesign Name:
) S! ]- N+ Y! e7 ]E:\Hi3515FJ_CADENCE\hi3515fj.dsn! C. |8 r5 T( b+ G, x* {3 ~6 R: k
Netlist Directory:$ c( U1 N2 o; F2 K- L% x
E:\HI3515FJ_CADENCE\NETLIST
) i) s% M* E( M' T1 pConfiguration File:5 t% M3 a, f9 H" H
D:\Candence\SPB16.2\tools\capture\allegro.cfg% h" Y2 L1 j) C$ \) E9 y' @3 V
Spawning... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"7 U& |/ ~3 @ s2 M4 G2 f
#1 Warning [ALG0016] Part Name "PHONE JACK-4_0_PHONEJACT_4_PHONE JACK-4" is renamed to "PHONE JACK-4_0_PHONEJACT_4_PHON".
3 j$ W2 |8 _0 s. e3 q. r+ k#2 Warning [ALG0016] Part Name "SN74CBT16214_0_SOP56-20-250-550_SN74CBT16214C" is renamed to "SN74CBT16214_0_SOP56-20-250-550".
2 V/ y) T7 R) W: FScanning netlist files ...! e$ \% U' D$ V2 n
Loading... E:\HI3515FJ_CADENCE\NETLIST/pstchip.dat
2 {1 D* f+ s0 K; @4 ^#248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'. Each section must have at least one non-common pin.0 x/ L- E" A/ a/ O5 d
Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.
. Z# u1 ^% y6 Y0 a ERROR(SPCODD-47): File E:/HI3515FJ_CADENCE/NETLIST/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again.
" s! O3 D/ Z* p: i2 d#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schema
5 V3 z9 H! l( {$ n: btic and rerun packaging.) i% f7 S- H$ L
#3 Error [ALG0036] Unable to read logical netlist data.% N9 L& Z/ r0 G: P+ F% ]: D! z8 |! S
Exiting... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
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! b5 _. Z% u6 q3 M3 Q0 I3 D ^*** Done *** |
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发表于 2011-6-12 12:00
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