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library IEEE;$ I( A. S0 o: r# O
use IEEE.STD_LOGIC_1164.ALL;
8 j+ X, K |+ j$ b |use IEEE.STD_LOGIC_ARITH.ALL;
. q8 _- q5 Y5 d, G8 Q W+ }) ?use IEEE.STD_LOGIC_UNSIGNED.ALL;/ Y/ k' I- _1 K+ I6 N
entity spi is
# m; q W1 T1 U" \2 d1 \port
/ n- G+ E) {1 V1 R' Z (
& d3 S3 l% g1 E+ {* `; G reset : in std_logic; --global reset signal
$ C! Z: C8 W2 m' } sysclk : in std_logic; -- systerm clock
5 J& d p/ E0 Z" C$ o data_in : in std_logic_vector(13 downto 0);7 s8 J" b; ^* k
spi_o : out std_logic;
0 `6 w4 V: o" K+ R sck_out : out std_logic;
/ z5 M1 r/ A9 Y s8 q ss_n : out std_logic_vector(1 downto 0)
+ R+ H, g" Y! [0 ]4 s F6 c R' d );
+ h! q, x, J9 fend spi;/ D0 e8 `& s1 D( M! d
architecture b of spi is# L. a9 b9 B( K
type state_type is (idle,shift,stop); -- data type define* l! { L a7 c6 m# H# G
signal state : state_type;+ t$ X; ^# r: n% z
signal out_reg : std_logic_vector(13 downto 0):=(others=>'0');5 ?2 H" W) M8 B, b% Z& y/ L/ d
signal clkdiv_cnt : std_logic_vector(3 downto 0) :=(others=>'0');9 P& ?: x) A% M$ W# A- J
signal bit_cnt : std_logic_vector(3 downto 0) :=(others=>'0');
( r# Z+ h( I$ K. a9 [ signal sck_o : std_logic;
) b# N% {; t7 }% A' ^# l0 o signal full : std_logic;8 p* w/ H! A+ m; q; A
/ _$ R2 j# s- l0 e+ T' R
begin
: I; F; J; M. s6 X7 n3 J sck_out <= sck_o;; m) ~3 U' C+ y! l: V# o. _9 t" ~
process(sysclk)! \$ d# l; s9 W9 _3 ^/ ]+ j9 E
begin! S0 s. k B7 q7 m/ m3 u
if (sysclk'event and sysclk = '1') then --reset
4 A/ r, E& X! z if (reset = '1') then
4 `9 w6 m2 F4 B4 R$ L/ b ss_n <= (others=>'1'); --AD5553 idle CS =1# j7 W$ ?; [* L# J1 B& ]
out_reg <= (others=>'0');6 C; V4 y n; A) G
clkdiv_cnt <= (others=>'0');8 s6 N5 g2 C$ W* j! R( k& N5 Z
bit_cnt <= (others=>'0');
' K- R' W* v# d$ f# ^9 T4 k- g" @! s2 D spi_o <= '1'; ?( i/ F2 }, X" {: ?" h9 l- O
sck_o <= '0'; -- AD5553 SCK idle is 0
$ {& \) _+ b" C state <= idle;
; {+ E" A$ b4 R4 r3 T1 `, S full <= '0';+ ^$ T3 \* O* e! n: {$ L
else " ^3 N' D& Y* r
if(full = '0') then2 f! w/ r3 [5 J. Y% K4 X
out_reg <= data_in ;) ]- ~, P1 t6 P- k# f: O* q9 }
full <= '1';2 D. j6 Q3 J+ T' {1 \
end if;
/ b1 j9 r" C; n/ Q$ Z9 q/ a# l) s 4 }) w* {; Z9 _& I$ U6 I9 V
case state is
' Q. R# q0 i. F3 c/ t. \ when idle =>
# g( z5 `9 J6 _3 @5 a
, Y9 c6 {1 U# J( f' @, \& J state <= shift;
% I6 K% i' x' D9 r h' b9 }. {1 V+ Q spi_o <= out_reg(13);- b# o& X4 T" x, F3 ~1 ~' v% ^
out_reg <= out_reg(12 downto 0) & '0';
* W" B& ^2 ]4 [' _ sck_o <= '0';
4 r- ?+ X+ |+ _# U) {# ?, ]) K) i when shift =>
7 |7 c% O( N" f M$ A) K/ d/ }" t; L clkdiv_cnt <= clkdiv_cnt + '1';) u b4 l; T" D5 |( E0 l& A4 B
if (clkdiv_cnt(2 downto 0)="111") then
" B( `) d% a7 }" z5 M sck_o <= not sck_o;
9 ?2 q, V$ t# i end if;% C' q: X3 L- Z, `6 z
, Z' @# v9 o7 M5 z0 v+ `
if (clkdiv_cnt = "1111") then* H) ^. C R& C% d
spi_o <= out_reg(13);
5 m# x- I5 [- `# ?# |8 i1 f6 m+ S out_reg <= out_reg(12 downto 0) & '0';6 q0 `' |% H- u5 N
bit_cnt <= bit_cnt + '1';( B, F1 J+ ]3 |: L* H* p
end if;
3 O. o- J3 h; [
( E+ v2 l4 a# y if (bit_cnt="1110" and clkdiv_cnt = "1111") then7 I1 l v1 x6 |. o1 e& x* J* m
state <= stop;0 E( H3 p# d0 J' A' t1 w
sck_o <= '0';
3 e/ P6 m6 B6 v d spi_o <= '1';7 d: J5 @$ e8 f; u& o7 a
end if;
. N! [( A. B# Z
! g! V8 L4 ^+ E& n5 ?3 H when stop =>+ g) U8 p9 q" u. S
state <= idle;
3 l0 g8 d) g9 q# U# ^- c sck_o <= '0';. \1 h& I2 V$ {
spi_o <= '1';: c* R. }9 i; D$ M3 O
clkdiv_cnt <= (others=>'0');
! [) ^$ ^; D; Q bit_cnt <= (others=>'0');4 n- m7 a! z1 F* a$ ?3 z+ ~
full <= '0';
. J) I8 Y# d' B4 A# [ when others =>
+ f# B0 I9 N3 m$ A: f state <= idle;$ G9 P: {7 L) p6 `) T
end case;" o& r. M1 X. l
end if;; c) a. e5 K% L) [
end if;7 ^9 G; H: j9 J
end process;4 D9 m8 G$ G7 ^3 ?5 c# L# v
end b;) C- i$ Z/ c; d6 j4 W& z
1 k: ]- `& D8 y! V
- m7 {" m7 e9 P+ e9 i其中out_reg 一直是0,在idle状态赋不上值,大家看是怎么回事6 Z- [4 V' D! S+ H7 M# q
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