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2# Allen : F' s6 v6 t) y) \) _# e
打开sigxplorer一点都没问题,并且也可以用它打开.top后缀的拓扑文件,且可以进行编辑仿真,但就是不能用它从constraint manager 中提取电路拓扑。当在constraint manager 右键sigxplorer提取拓扑时,会启动sigxplorer,但不能提取拓扑,且allegro si 就会提示:: I) M1 c$ J7 r8 Z% ?
Finished loading SigNoise device libraries
1 f/ k% {# A, uUsing working device library 'F:/candence/PCB工程文件/Minisystem/devices.dml'
9 f! G8 R4 T/ |; j" B) ~Loaded existing Interconnect file 'F:/candence/PCB工程文件/Minisystem/interconn.iml'
# @) M1 _6 A7 \& x- C: n2 x4 gFinished loading SigNoise interconnect libraries
7 D5 M8 S# G0 W% wUsing working interconnect library 'F:/candence/PCB工程文件/Minisystem/interconn.iml'
2 g0 @& N& Q+ p8 ^+ e- pLoading sigallegro.cxt , F5 L. g8 `$ q6 p
Loading axlcore.cxt 2 [5 b) j+ h C' u+ g( U h5 P- F
Loading skillExt.cxt
* Q; c F; s& ?# j& L! H9 \' F! z7 non-encrypted models saved to file F:/candence/PCB工程文件/Minisystem/sigxp.dml2 k B+ f" Z8 ?
7 models saved in sigxp.dml, r, O+ O# E/ b
请高手指点下 |
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