Verilog七人表决器有点小问题该怎么办呢

bikong7 · 发表于 2010-4-3 17:43

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七人表决器的程序如下
module voter7(
output  reg pass,
  input[6:0] vote
);
integer i;
reg[2:0] sum;
initial
begin
sum=3'b000;
end

  always @(vote)
begin

for(i=0;i<=6;i=i+1)    //for语句
begin
if(vote[i]) sum=sum+1;
end
if(sum>3)  pass=1'b1;    //若超过4人赞成，则pass=1
else       pass=1'b0;
   end
endmodule

有提示是这样的
Warning (10235): Verilog HDL Always Construct warning at voter7.v(18): variable "sum" is read inside the Always Construct but isn't in the Always Construct's Event Control

Warning (10240): Verilog HDL Always Construct warning at voter7.v(13): inferring latch(es) for variable "sum", which holds its previous value in one or more paths through the always construct

仿真的时候pass信号为未知状态
怎么办呢？