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DATE: 05-14-2010 HOTFIX VERSION: 0088 Y& n* w9 R- q: c& t9 W7 D( |
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. l6 H4 W7 c$ n2 i8 F+ gCCRID PRODUCT PRODUCTLEVEL2 TITLE
5 ~- }, Q' K+ a* j, @===================================================================================================================================
( c" ^( K/ ^! ~2 ]0 G697699 CONCEPT_HDL HDLDIRECT SCM Verilog output contains the line 揹efparam <instance number>.SIZE
6 [; d" V$ c: t. e9 K734169 ALLEGRO_EDITOR PLACEMENT Wildcard asterisk character giving "illegal char(s) in refdes entry." error in quickplace.2 ]* J& Y0 X% r* p7 f# {5 Y
738970 SIG_INTEGRITY GEOMETRY_EXTRACT power bus issue with SSN simulation when device is on bottom
/ ^# |# v. e2 I8 y744762 CONCEPT_HDL OTHER Connection dot sizes do not match on printout vs. screen. r6 A5 u. J# C( x5 T6 \1 {! y
750371 MODEL_INTEGRIT GUI Model name in physical view cann't match the model in right workspace
3 C' Q9 K$ C& }+ S% u7 D$ c757024 CAPTURE STABILITY Capture crashes while exporting to EDIF" \- r6 s; n% Q* g
759094 CONSTRAINT_MGR INTERACTIV One member of a diff pair will show Analysis Failed when analyzing the design.
1 x$ @! B. p) ^( r# B1 @760178 ALLEGRO_EDITOR EXTRACT Crash Allegro when executing extracta command for big size design(size of .brd. c; h; A, `) ~3 x
761391 SIG_EXPLORER OTHER Incorrect rise time
d+ [! Y$ R0 F2 a3 R762402 ALLEGRO_EDITOR MANUFACT When photoplot(RS274X) of MM unit was loaded, shape was broken.0 C% J4 z+ `* u2 ?: Y: q. A
762783 SIG_EXPLORER INTERACTIV sigxp - coupled tline on stackup layer should show solved impedance
6 a0 Z: R0 M5 T0 x) l" o! ?763150 ALLEGRO_EDITOR OTHER Request - IPC356 output truncate the padstack size to fit into the columns 59-62 and 64-67
! {+ z p! L0 u; |763556 SIP_LAYOUT ASSY_RULE_CHECK Assembly Rules Checker is displaying an array of confusing DRC's on a Soldermask shape.
% c D- D) @. v& q. w/ L764399 SPECCTRA ROUTE Manually routed trace in Allegro are ripped OFF after routing in SPECCTRA using Route > Route Editor.8 q+ O$ p3 M; y4 S& E" E, ]7 e- p
764475 SIG_EXPLORER INTERACTIV topologies from earlier versions cannot be opened in 16.2 on a machine) o- E- u( Z$ o0 b _5 e& O; t
765287 ALLEGRO_EDITOR PAD_EDITOR attempting to open padstack fails with - database has a non-recoverable corruption.
; c1 u3 z6 z/ a( n! y766041 ALLEGRO_EDITOR OTHER Auto B/B via generator incorrectly defines some BB vias
; v/ f, j B3 z$ C$ r766153 ALLEGRO_EDITOR SKILL Allegro crashes when trying to extract padstack information4 w) {4 y3 x* l
766611 ALLEGRO_EDITOR EDIT_ETCH slide creates DRCs in ARK area
& J" y0 m4 ~% ?3 K) q, s" |767041 CONCEPT_HDL CORE The tap command failed because the specified tap body CTAP is invalid% b+ t& k: ~2 W( c( r! Z- u; s% W
767146 FLOWS PROJMGR Project manager open last open .cpm in 15.7 version not in 16.3
$ t7 `* c- {3 h6 U8 ~5 h767526 FLOWS PROJMGR Project Manager customization does not work6 c E1 C1 q5 Q- Z) Y# v+ C0 O
767671 APD DATABASE Crash creating cline with axlDBCreatePath() on this database.
# C. r) P( j! I& C' C! ?767951 ALLEGRO_EDITOR DATABASE color net param file omits nets with bus brackets in the name6 Q* @6 v+ ^2 q0 W( W+ Z8 t4 c
768168 CONCEPT_HDL CORE Fontsize on instances changes when doing backannotation
5 U7 N/ r0 R6 t8 @2 M4 e1 }. s768207 CAPTURE STABILITY Capture crash while editing properties
* \. l5 R* t% G8 o+ F768734 CAPTURE PROPERTY_EDITOR Properties of title block are not getting editted through spread sheet.
! R1 _$ O. M: }8 O" L$ q p768832 APD DRC_CONSTRAINTS Following Performance Advisor instructions results in much longer DRC check time.% W2 @( { r! W+ F) H0 i6 g
768990 F2B PACKAGERXL RFSIP architect 16.3 85Y Schematic to SiP fails due to softinclude in cds.lib file this problem does not occur on 16.2
+ d% }0 I8 X u' c' \& o' V769097 SIG_INTEGRITY GEOMETRY_EXTRACT Sip Digital SI-Bus Simulation function will shut down auomatically when it is running
. ~ D2 S1 f1 K3 `0 y769235 SPIF OTHER need to be able to remove mbs_spif* properties added by mbs2brd2 ~" k- t2 f+ t# V9 e5 ]: m
769326 CONSTRAINT_MGR DATABASE Length by Layer crashing
+ { c* [& ^! O4 P769336 ALLEGRO_EDITOR TESTPREP testprep density - returns Unable to add the PROBE_DENSITY subclasses.
Q, c/ |+ H+ F7 |# z769458 ALLEGRO_EDITOR OTHER SMD Jumper has a problem about the connection point when using the Add Jumper( J9 G. O# W2 k8 S. O' f) @
769845 ALLEGRO_EDITOR EDIT_ETCH Diffpair routing out affected by line to line spacing rule.+ m, k e$ G4 d( Z& [ Y- P2 T3 V
769934 SIP_LAYOUT WIREBOND Duplicate Finger Name.! c3 B0 R. |$ }# t
770006 ALLEGRO_EDITOR OTHER Ratsnest_schedule[Power_AND_Ground] can not show figure without move symbol.% s. p) y" W3 g9 w$ w3 O
770125 ALLEGRO_EDITOR DATABASE PCB SI GXL Via Labels grayed out on formand labels not visible on the canvas
, q' w- N1 f+ V4 b4 F m770212 ALLEGRO_EDITOR DRC_CONSTR Incorrect Etch Turn under SMD pad DRC error on this board Q! L, G; X/ A/ @) W* ]
770230 ALLEGRO_EDITOR ARTWORK Artwork fails to suppress unconnected pads on pins with the net_short property./ ]2 U3 N6 e1 _! D* J% e! E9 o' n
770233 ALLEGRO_EDITOR MANUFACT Fillets are not behaving as intended.5 l9 |/ z6 S- g* J; Q* n' W1 L
770442 SCM PACKAGER Error during Export Physical - The subdesign block instances ares not updated with reuse properties
+ m5 M" B+ ^" e7 D% ?! k, B( c770556 CONSTRAINT_MGR ANALYSIS PCB Editor's Constraint Manager not updating custom constraint cell.
( r& C9 q! s! d( K2 g770861 ALLEGRO_EDITOR PADS_IN PADS translation fails with no error message% ^6 e% C$ a6 R
770872 SIG_INTEGRITY OTHER Opening Orcad PCB Editor for this board takes Performance License as well
; w* x. e }4 z5 s771117 ALLEGRO_EDITOR DRC_CONSTR Allegro PCB Editor crashes on Update DRC-16.3/hotfix006
( K* D5 L5 M" T+ m8 V/ j4 q2 j771181 ALLEGRO_EDITOR PLACEMENT Component deleted completely from board file after we Mirror and rotate them while moving them." K- ?( G1 d+ e2 `# n
771256 ALLEGRO_EDITOR DRC_CONSTR Update DRC consumes system memory and crashes allegro after approx 30 minutes' l3 v, R0 Q7 h- V
771423 ALLEGRO_EDITOR SHAPE Shapes - Update to Smooth - Low on available memory please exit the program.5 ^ R' |/ W. f( A/ k$ H) f( @- U& A
771456 ALLEGRO_EDITOR EDIT_ETCH Allegro 16.3 crashes when using arrow keys7 W; I8 e2 p% Z* W
771719 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license.
5 ^8 G, y) z7 u: D+ ^& [771765 ALLEGRO_EDITOR PADS_IN PADS translation fails to translate symbol$ C$ b. j# f6 m" s; _
771766 ALLEGRO_EDITOR DRC_CONSTR Moving certain components takes a long time on this board database.( f6 T9 n N4 K! J1 o' x) _1 w w
771815 SIP_LAYOUT IO_PLANNER SiP OA co-design flow does not allow a save to the .sip file after modifications in IOP
# a* D; W* Z% I+ L5 L773072 SIP_LAYOUT ASSY_RULE_CHECK wire to wire same profile
5 P9 E) F6 T1 O" }, }773126 CONSTRAINT_MGR UI_FORMS Constraint Manager "Value Filtering" for Topology Schedule is missing TEMPLATE and "UserDefined"
) p: w9 k* _- c+ ~7 Z6 A7 q773179 ALLEGRO_EDITOR PAD_EDITOR pad_designer crashed when attemting to delete internal name layer.& r1 ?4 o2 P3 E: z
773229 ALLEGRO_EDITOR OTHER Netrev never end importing netlist generated from Capture CIS
7 J( D, ^5 V5 {4 ]4 x6 M" i# g773329 ALLEGRO_EDITOR MANUFACT Allegro closes when performing a Linear dimensioning and then selecting the undo icon.
' I' t' Q T) s6 \0 C773483 ALLEGRO_EDITOR MODULES place module problem
3 O0 D3 v, V& @3 R3 N2 [774036 ALLEGRO_EDITOR INTERACTIV Rats not shown after move->mirror command! ~% s' ~! N/ u7 C7 n# U" R' x
774170 ALLEGRO_EDITOR DATABASE DBDOCTOR fixes Error but it reappears and Artwork fails @1 h; } U/ d: `0 X: b% D
774602 SCM OTHER ASA crash while working with hierarchy
) x g; q9 I: p9 H- m4 c774643 CONCEPT_HDL CORE DEHDL crash on edit of attributes
6 v' K; a$ O# v4 t775201 ALLEGRO_EDITOR SKILL Color palette can only be changed one time using skill commands e7 o+ C2 r. k
775815 SIP_LAYOUT WIREBOND Unused wire profile once purged using wire profile editor are still available in CM and Color dialog
) _6 ?& a) M$ a* S7 ?775826 SIP_LAYOUT WIREBOND Cannot change the Wire Profiles on the wirebonds in this design
. {" x: f( u$ N. k7 Z. R. z775842 SIP_LAYOUT WIZARDS Die text in wizard is changing DIE location when origin set in DIE text file is other than 0, 05 k/ a) H& Q* n% M; M9 [
DATE: 04-23-2010 HOTFIX VERSION: 007
' M c' I0 J! r2 V" d) D===================================================================================================================================
# y9 P* j% t6 ~0 T( lCCRID PRODUCT PRODUCTLEVEL2 TITLE
- {0 L5 I& H' k===================================================================================================================================
+ x a# n. s8 U# |9 J721859 ALLEGRO_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why?) B8 k: g2 m/ B; o/ @9 O. }
740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp
/ ~; F* H% s1 \* [744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools/ Y; j2 D) X0 A5 P, e
747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0., ?, s7 Z$ `7 A9 \- c$ ]
747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash., n0 p* E2 B: D
751372 CAPTURE OTHER Copy / Paste Issue in capture 16.3
$ B$ j( G7 I& ^4 u: L( Q4 v }757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit.
$ O L5 T( t2 y% J/ a( a' z759906 CIS PART_MANAGER Property copy from one to several parts doesn't work- _+ t5 ^( e8 S0 h; G$ a2 S3 G
760154 PSPICE NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result
" X, D1 y+ U2 c761177 CIS OTHER Error Message - Memory exhausted2 E0 a' o" b0 h* T4 |" |5 o
762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location., F! l- S- E1 G W9 Z
763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.
9 m; O- G( A* m- P763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created.8 W5 q8 x8 `' F9 z: _. Z" F
763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager?
* d; e$ N# F* g) S, {7 T; Q764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.3
4 i$ E0 S$ [( x764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle.
( \0 @2 S, b+ R' e6 I/ u' z/ Y, x764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad/ n* @0 u4 E' L
764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.3* P E w$ R4 o) f; k- n
765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro
; d) P9 m0 A: s2 p9 @9 L+ }" t765319 APD DRC_CONSTRAINTS Identical Constraints in Performance Advisor question
' N7 W8 y* ]4 [# i' k3 u" A765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape.9 j a6 v$ e/ ^( Z: O
766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle8 x7 u& x: m \* L& [
766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design
" _2 s0 p: P; J3 T, S766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.3
$ y- g& ~! b/ y7 [! D766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit+ r6 X# t& V; d5 S. q" S. L
767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version.) j: N6 N/ W7 ]: B0 j- z6 r. H1 C9 k
767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step.
9 M& V+ h9 D- x) R& m# B767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs.
4 I2 t' O: h; d7 {* V3 o767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly" n# Y1 s! z8 D- w
768822 ALLEGRO_EDITOR SKILL axlSetParam return value is divided by 10 to the power of the design accuracy.2 |- @3 Z. C3 I
769150 CIS PART_MANAGER Update All part Status on a group changes 揇o Not Stuff?status to 揝tuffed?in V61.3_ISR_5.
" e ?; H- Y( W% o6 ADATE: 04-09-2010 HOTFIX VERSION: 0069 b5 b3 H& j4 g- D; F
===================================================================================================================================
/ A- b2 g2 ^' j' \' ~/ NCCRID PRODUCT PRODUCTLEVEL2 TITLE: \3 E& q. _6 l$ R4 j
===================================================================================================================================" W2 v) c2 r' G- O
745241 CONSTRAINT_MGR TECHFILE Importing a tcf file automatically enables On-Line DRC.
0 m1 W n/ }2 Z+ H5 E$ G3 U752587 ALLEGRO_EDITOR PLACEMENT Uppercase File name(XX.mdd) for Placement replicate update on Linux.5 }! i9 f Y" O* F- R9 Z) f- ^& m
753626 CONCEPT_HDL CORE newgenasym error while saving the hierarchical block symbol& k: t# Z* a/ x) j' H* j
753894 CAPTURE OTHER Case sensitive version control S/W' G- i r0 `% e- w2 L, V* Z
754487 RF_PCB OTHER Various asymmetrical clearance problems uncovered - calculation issues?8 Q' u( W% F9 ~# p+ f1 D
758272 CONSTRAINT_MGR UI_FORMS Entering values on the Min/Max Propagation Delays worksheet hangs the application.! j4 _+ d6 R1 O9 G9 C2 m O% L) I" L
758911 PSPICE PROBE Pspice crashes while exporting probe data using our sample project
: U: U" u. `5 g4 P759871 CAPTURE PROPERTY_EDITOR Save option in Right Mouse Click on property editor of nets doesn't saves all the changes.' V# k9 e0 w. [: b5 E/ w
759890 SPECCTRA ROUTE Specctra autorouter ignoring prerouted nets- y1 G3 U5 w( s; `: c
760067 ALLEGRO_EDITOR SHAPE Dynamic Shape not getting filled on board with odd angle placement and routing
# M& _4 }7 x1 r, m760284 CONCEPT_HDL CORE Update Sheet Variables turns of the grid$ q: I; @ F% D' q
760480 MODEL_INTEGRIT OTHER Message open clipboard failed when trying to open the rename/reorder dialog in Model Integrity
' ]3 w6 X& w* i. n6 H' H760667 ALLEGRO_EDITOR PADS_IN The pads_in.exe translate incorrect drill shape from PADS 2005 ascii database.
4 B: g2 f7 Q4 k y7 O3 N$ }760741 ALLEGRO_EDITOR MENTOR mbs2brd does not work in 16.3 but works in 16.21 C: z4 \5 n; l& c6 o
760810 CONSTRAINT_MGR INTERACTIV Deleting Region Deletes NCCs
, x/ i2 K, z2 ?7 i2 p2 l) }$ Y761114 PSPICE PROBE Refresh issue in Display > Cursor window
$ S. F b: w) r' r; s0 q761180 ALLEGRO_EDITOR DRC_CONSTR Via_at_smd not working for custom shaped padstacks.* W5 s& K8 A7 l5 e, b
761305 SPIF OTHER Allegro crash when seleting any of the Route - PCB Router - submenu items.. P8 k3 X4 m2 x' q% e
761376 ALLEGRO_EDITOR PAD_EDITOR Wizard_Template_Path is not considered for symbol template look-up ?
0 ]5 R& {$ n* H3 i761416 ALLEGRO_EDITOR DATABASE Allegro crash on chaning the subclass for group of clines, X q/ `8 E$ ^: ~* r
761492 ALLEGRO_EDITOR SKILL about axlTransformObject function. K7 a9 B) Q, [
761518 F2B PACKAGERXL about mismatch library path between cds.lib and actual
' i% ?/ _; ~+ O761737 ALLEGRO_EDITOR OTHER Running Dbdoctor after executing Skill is giving symbol fit error for the .dra file
! [" D; {- k; W/ t) _- c762155 ALLEGRO_EDITOR SYMBOL Updating a symbol changes the netname of the cline resulting in drcs.
1 Y+ o* P( P+ B0 K) E- N/ S' u8 S762181 ALLEGRO_EDITOR OTHER Allegro netrev crashes for long device name in PST* files' k9 G2 \/ l- _, L) o5 v" `+ O
762316 ALLEGRO_EDITOR MANUFACT Allegro disappears on Adding dimensions for the symbol file9 u# Y! ~7 w3 C( u6 u4 J
762792 ALLEGRO_EDITOR PADS_IN PADS_IN fails for SPB 16.3; Z/ x, E7 ]6 v5 Q
763108 ALLEGRO_EDITOR SHAPE Z-copy shape create an error like VOID boundary may not cross itself
; n( a4 W9 H8 q1 K! o! p8 K763134 SIG_INTEGRITY SIMULATION Bit 7 of a simulation is out of sync with rest of bus. It should be the same for all bus values./ Z" C P; J$ l" F# |* F( {& ^" {
763149 CIS GEN_BOM CIS BOM in V16.3 is not correct if database has Quantity field and its value is 0.1 W; E6 h2 F' {) u9 U
763296 ALLEGRO_EDITOR REFRESH The error was happened while doing the SUM
2 B9 G3 m6 \$ H q. x763303 ALLEGRO_EDITOR OTHER SMD Jumper has a problem while using the Add Jumper
: s- v7 I! C- Z763315 ALLEGRO_EDITOR PADS_IN pads_in got error message WARNING ERROR(SPMHDB-205)6 o0 n# r6 o; t6 z
763354 ALLEGRO_EDITOR PADS_IN Auto suppress redundant shape while using pads_in translator
: E9 Q5 B& i- V C763428 ALLEGRO_EDITOR PADS_IN enhance pads_in.exe translate spacing and physical rule into Allegro.+ I$ g0 k* c& E) C
763446 ALLEGRO_EDITOR REPORTS missing fillet is reporting pad without drill. r& B4 S' k- G; [
763448 ALLEGRO_EDITOR DRC_CONSTR Performance advisor shows Cset as unused nets when it is assigned to Diff pairs or xnets.
8 I2 V. X* e M3 g! R763586 ALLEGRO_EDITOR DATABASE Allegro rounds off the value after decimal in CM
i+ G9 U, u* Z+ F7 l" u! A. }3 K764077 CONCEPT_HDL CHECKPLUS The output predicate in the Graphical environment is not always returning the pin object for an output pin.
, @1 r, \! q$ U( _" I: o" w2 V* m9 z1 @DATE: 03-26-2010 HOTFIX VERSION: 0056 X, U9 x# d( P4 [; ?8 Q6 }
===================================================================================================================================
% N* T& f9 f8 p+ `1 K# sCCRID PRODUCT PRODUCTLEVEL2 TITLE
" P3 k: n; \( g( [; Q===================================================================================================================================
$ V2 \' J, s! o) s! s% w( O599819 SIP_LAYOUT 3D_VIEWER display soldermask by default in the 3d viewer/ {- B5 l* a: a4 R, x
735992 CONCEPT_HDL CORE Create Test Schematic does not use the correct package type
8 T# ]: D' k) k743787 SIG_EXPLORER OTHER 16.3 SigXP crash if sigxp.run created by previous version exist.8 |# e# I8 c0 x4 k- }" C
746320 CAPTURE NETLIST_ALLEGRO Remove Semi-colon from invalid pin-name check during netlisting0 s8 R- }) e" ]7 d7 z
746444 ALLEGRO_EDITOR OTHER show element fails to display info on a via if it is in a module.
7 g% m* D. @: w/ y( h746726 SIG_INTEGRITY SIGWAVE Save As and Open Dialogs open in last saved directory/ ]. M4 }8 I! R5 u6 P
750080 CAPTURE NETLIST_ALLEGRO Improve error message ERROR(SPCODD-390)( K, G; H" c( F7 D9 i3 f3 G
750606 SIP_LAYOUT ASSY_RULE_CHECK Wire to BF same profile check+ l' e, d, Y! z: Q: p% h& ]6 C8 F: b
751492 CAPTURE FPGA Option to swap the pin-numbers rather than their locations in the Schematic after back-annotation
* D% q! T5 N4 ?, B! R753834 CIS LINK_DATABASE_PA unable to link multiple database part+ W) ^/ ^- p8 g) ]1 ^' V; x: }
753990 F2B PACKAGERXL Delay in opening the subdesign tab in the Export Physical setup in SPB 16.3
* ~- n" k; G! k754328 LAYOUT TRANSLATORS L2A gives error Subclass name TOP not valid Allegro subcls with s029 hotfix
! {& o3 J n- I* c8 D9 D754434 CONSTRAINT_MGR OTHER allegro crashes when deleting matched group* L% X7 C- b4 p. A! U' F; B
755111 ALLEGRO_EDITOR INTERACTIV "ALT_SYMBOLS_HARD TRUE" property does not work when I mirrored symbol using move command in 16.3.! ]$ i8 R. s& e( \6 c
756131 PSPICE SIMULATOR Capture crashes while re-running simulation
/ C1 N2 A% `5 M) O& P$ X5 o$ t; t756148 PSPICE PROBE Zoom Area in Probe Window does not work for digital signal in SPB163$ [1 x$ T& R+ ?+ H. K3 g+ M
756169 SIG_EXPLORER OTHER Signal Explorer crashing due to sigsimcntl.dat
+ u7 c( V8 r% g- n! z756176 PSPICE PROBE Trace color is wrongly interpreted in PSpice probe window.
' ~$ E$ [9 C4 S6 ?" h6 H6 t756224 SIG_INTEGRITY SIMULATION Simulation aborts reporting that VIA models have changed; v( P+ j& ?9 u
756281 ALLEGRO_EDITOR OTHER Why *.sav file cannot be recovered from PCB Editor utilities?
) c) I- s: K6 ^" j756673 SIP_LAYOUT ASSY_RULE_CHECK Running ADRC Metal to metal checks causes false X-D DRCs, cannot clear them and trying crashes the tool) O* ^) P% n! {* ?
756918 ALLEGRO_EDITOR OTHER Allegro angular dimensions working incorrect in 16.3' J, d _; i, }7 u0 N. ?1 U/ ~) h
756932 ALLEGRO_EDITOR CREATE_SYM Create symbol fails with error duplicate pin number
' m+ X; h$ |6 J- _0 u756976 ALLEGRO_EDITOR SKILL axlChangeWidth always return nil in Allegro version 16.3
6 _. C" b$ e2 M" N) a& S757000 PSPICE NETLISTER Incorrect Hierarchical Format Netlist created' u' l: ?8 n7 s, V
757406 APD OTHER Implement Segment over void features in APD L6 y) F( ]/ o3 v
757624 SIG_EXPLORER OTHER Sigxp runtime error when simulation is run and exit without saving the topology+ P2 P3 g: S- |+ f/ ~) K
757820 ALLEGRO_EDITOR SHAPE Shape does not void to hole if there is no pad
* o6 Q" y6 i4 I758009 ALLEGRO_EDITOR OTHER Export > Library (MECH_SYM) adds a new subclass NCROUTE_PATH, data moved from one subclass to another.: A0 W. e& H. E# U$ W% i# [
758022 CAPTURE DRC Capture crash while running DRC with 揜un Physical Rules?checkbox.
- v) I+ p0 Q2 X( b9 N s% y758190 ALLEGRO_EDITOR PAD_EDITOR PCB Editor crashing on pin move in this design6 ^2 f- F i- a! [" ]% h, @3 O
758374 F2B DESIGNVARI Problem with Mechanical part in Variant Editor+ t( d' q2 m. q( G* h, y. @0 H$ M
758471 SIG_INTEGRITY OTHER Differential impedance does not change on changing the etch effect values.
: [% y R/ K6 \3 g5 [758490 CIS CRYSTAL_REPORTS Different crystal report output in 16.3 than from 16.2
: q& k @% e' }8 j, o758498 CAPTURE NETLISTS PCB Editor netlister hangs* @! O! L7 i$ |1 H5 [ @( }8 E/ f) T; h
758584 APD SHAPE Shape not voiding all elements% r. j4 \0 v0 i1 z1 `
758886 ALLEGRO_EDITOR REPORTS Total number of nets is wrong into Testprep Report3 H; M6 r* k G3 t q& h' |
759146 ALLEGRO_EDITOR SKILL The title is not displayed in the form by the version.
6 d" Z5 u( w, F: S759339 ALLEGRO_EDITOR ARTWORK artwork output fails by SPB16.x." x5 ]3 e0 y5 K4 s0 ?
759591 ALLEGRO_EDITOR SKILL axlSetParam fails and does not round the value as indicated by the warning message
& O2 n0 e- l6 x, Z5 A: I759816 CONSTRAINT_MGR OTHER Allegro Hangs when double click on a Bus in CM9 n0 B, m7 s6 C, W& f
759947 APD OTHER Need an a way to convert Lines into Clines
. F4 ]. ], c" t K/ |) g760353 ALLEGRO_EDITOR MANUFACT Allegro crashes and creates a .sav file on running the silkscreen command from Manufacture > Silkscreen, F% x/ k" [/ D: H/ w3 M
760432 ALLEGRO_EDITOR PARTITION Unable to remove fixed property after partition import! s6 M+ w @3 r/ z" V3 W
760638 ALLEGRO_EDITOR PADS_IN pads_in translator can not handle " PINPAIRGROUP ".9 P9 r) o/ j: Y) V
760734 ALLEGRO_EDITOR SHAPE Different therma contacts on rotated partsl
0 m# ?. Y% Z7 B2 j5 q761436 CAPTURE NETLIST_ALLEGRO SPCODD-53 Error when creating netlist with PACK_SHORT
/ Z. a. U; O; E8 P! k# fDATE: 03-12-2010 HOTFIX VERSION: 004+ i0 `1 G4 V' P
===================================================================================================================================- _* {7 u" |# T' h3 ~0 T( U
CCRID PRODUCT PRODUCTLEVEL2 TITLE7 F' A' o; x, h J: U3 K
===================================================================================================================================
* c# @: k/ Q/ f% ~7 G* ?5 T689495 ALLEGRO_EDITOR DATABASE corrupt database- }, S5 N! u# d+ q7 m
725944 SIG_INTEGRITY GEOMETRY_EXTRACT xtalk make allegro freeze and never give hands& F, Q2 x! H, E
732604 SIP_LAYOUT SHAPE Shape Issue - added shape will not clear around other elements.# ]0 T* N' T0 x3 N& D
740106 PSPICE NETLISTER The "Enable PSpice AA Support for Legacy" option does not give the Desired Monte Carlo results
5 I5 F3 ?) e9 V744259 SCM UI Signal order reversed when a Vectored Signal name is renamed in reverse5 T% ?9 M$ J% D! Q! R! P
745554 SIG_INTEGRITY GEOMETRY_EXTRACT Time to get Xtalk simulation result in 16.2 is lower than acceptable by comparing the time in 15.7
/ g6 ]$ t7 r6 u) @745595 RF_PCB FE_IFF_IMPORT import iff RF_PCB give an empty block6 G5 _( J7 `* e* E2 n$ [
747133 CAPTURE STABILITY ERROR [DSM0006] Unable to save8 Q) A. y% I9 Y$ \' I9 T7 q- n5 i% ]
747679 CAPTURE STABILITY Trying to Save the Design in 16.2 format gives DSM0006 Error and crashes Capture
. a: ?( Z. B: ?750460 CIS FOOTPRINT_VIEW 3D footprint viewer doesn't shows the footprints
% a+ w) k1 H0 @; y" J750777 SIG_INTEGRITY OTHER Trace impedance showing wrong( O+ q# O) [: b ?2 I+ B! |, y
751424 ALLEGRO_EDITOR DRC_CONSTR Unexpacted DRC for Shape to Route Keepout7 {$ ~6 N+ J# J: D) |* U3 c( }
751897 SIP_LAYOUT SPECCTRA_IF Radial Router crashing SiP tool
4 d6 r3 c* }3 ]% S. t7 e752029 SCM OTHER Cross probing not working between SCM and Allegro Editor in Linux Environment
3 e& }3 z4 ]. i752450 APD PADSTACK_EDITOR APD crashes when selecting a User Definable Mask Layers.
2 |' I4 ]8 e6 r8 Y7 B4 X752581 PSPICE PROBE Pspice probe window crash6 N; t0 i/ `4 A' i w: S7 y% e
752709 ALLEGRO_EDITOR PLOTTING Sheet content doesnot plots title block
0 g' H. G; n4 [3 J6 ]8 ]+ _: G752908 ALLEGRO_EDITOR INTERFACES Output from Export > DXF shows one instance of a via on the wrong layer1 ~' c1 \+ @* o+ s0 B. O2 K; Y" q
753226 ALLEGRO_EDITOR OTHER File > Change Editor doesn't shows the default Product Options0 g6 s/ E4 l1 p& F
753622 ALLEGRO_EDITOR GRAPHICS Enahnce capture image command to default the save as location to working dir0 q" y. q1 O1 A F* E9 z: d; O
753773 APD WIREBOND Requesting the option to set the diameter of the default WB_TACKPOINT power ring pad.
, a% [5 P; @& H4 c/ s753778 APD IMPORT_DATA Import NA2 displays the design momentarily and then crashes! z$ [( l5 c& j* r+ j; n
753866 SIG_INTEGRITY OTHER about Select by Polygon after move command
4 Z" w/ N4 d+ o7 ?753958 CAPTURE OTHER Capture V16.3 is extremely slow while edting schematics of design placed on network drive via VPN.
7 `( d# O2 x4 A4 F) k754050 ALLEGRO_EDITOR UI_FORMS Why show element window disappears when scriptmode is set invisible/ ~2 E" P% i, x
754143 SIP_LAYOUT OTHER SiP Package Design Integrity - running Extra Cline segments generates report without Layer number
/ y3 n, B% n& N2 Z+ c; ~9 h754327 ALLEGRO_EDITOR OTHER Rename Sub Class is not working as desired.9 Y0 F2 J, a4 b8 k/ w, u% B& ]4 S) T
754364 ALLEGRO_EDITOR PLACEMENT Crash when applying placement replication# F8 I' |/ O6 B- c0 Q( Z
754462 ALLEGRO_EDITOR SHAPE Allegro circular dynamic shape fails to fill5 p0 V# @- v9 x$ R
754819 ALLEGRO_EDITOR OTHER Create details shows wrong graphics for filled curves
. E0 @+ D: V' J755176 ALLEGRO_EDITOR PADS_IN Pads translation succeeds in v16.2 but fails in v16.3 on this ASCII file% K& D7 w9 N3 o b8 G
755256 ALLEGRO_EDITOR OTHER Attached script is crashing the designs in v16.3
! J* d& U" S. F8 I755610 CONCEPT_HDL CREFER Cref hyper links does not work for signals where number "0" used to define the zone for page border& I' K4 l$ @: p4 E9 T6 w/ c
755787 ALLEGRO_EDITOR EDIT_ETCH crash using resize_respace_dp command# W& W) V- ?* K
755881 ALLEGRO_EDITOR DATABASE Swap component crashes application
. o3 ?, l' W4 c3 j756092 CAPTURE PROPERTY_EDITOR property editor flickers and loops on value edits
" Y& X i! P$ }1 a6 N1 `DATE: 02-23-2010 HOTFIX VERSION: 0032 ~+ ~0 G! d& A8 {' I' ?8 A# u3 l
===================================================================================================================================
, x4 t! |2 c1 o oCCRID PRODUCT PRODUCTLEVEL2 TITLE8 m9 Z M" O' X7 J
===================================================================================================================================
+ t; y6 i% G" f+ W263504 CONCEPT_HDL CHECKPLUS Checkplus fails to run if crefrpt exists in the design
4 Q$ m$ i+ M' R( B$ v6 j726836 ALLEGRO_EDITOR SKILL axlGeo2Str() and axlGeoEqual() return different results
! K; K' `4 b4 V* ~3 I% ^730820 SIP_LAYOUT PADSTACK_EDITOR Changing the Via diameter will cause the SiP tool to crash
2 k Z5 f- ^; @( N+ V" S735193 CAPTURE FONTS Pin_names and Pin_numbers get convertred into darkened blocks in 慫oom to all?view in V16.2.
8 ]( W5 H! @2 S737307 SIG_INTEGRITY GEOMETRY_EXTRACT differential pair extraction to sigxp fails to extract coupled sparam via models
8 Y. i! z7 ?) J5 `740936 ALLEGRO_EDITOR SYMBOL Confusing error message during Create Symbol
, j( b1 b! [/ H744191 ALLEGRO_EDITOR EDIT_ETCH Arc routing enhancement6 ]& Y0 }5 z0 w H# z
744497 ALLEGRO_EDITOR INTERACTIV PCB Editor Crashes with Data Customization Feature: |6 r/ l3 h% r7 u( L1 Y3 b+ D( _
746572 ALLEGRO_EDITOR DATABASE Reoccuring error in attribute pointer to attribute invalid on dra.! E: M7 h- }/ n$ r1 Z+ ^3 T% T, K
746978 SIG_INTEGRITY SIGWAVE 2 licenses were used for SigXP and SigWave.
+ N! h9 s6 R. s5 |! ^: d747219 SIP_LAYOUT SHAPE Dynamic Filleting not working with odd angles
V1 [0 \9 H" W4 l" X4 `, r747593 ALLEGRO_EDITOR PADS_IN Some RULE_SETS cause the PADS translation to fail.+ t. E& u2 c( T2 R2 `. N
747746 ALLEGRO_EDITOR OTHER Request for more detail in downrev.log file) l. l1 t( n2 w$ L/ ]& ^
748033 GRE IFP_INTERACTIVE Enhancement in GRE where Show Element on Bundleshould show the total number of nets that are part of the bundle7 F y1 W J3 @3 n$ D
748333 ALLEGRO_EDITOR OTHER place by schematic page number not showing pages correctly6 m5 L V9 F0 }' n* N3 _% o3 l- W
748375 ALLEGRO_EDITOR MANUFACT gloss - line smoothing causes crash
5 Z7 v5 K y" a4 {3 k' J748818 ALLEGRO_EDITOR DRC_CONSTR Undesired DRCs shown in allegro 16.3 while moving component and the same are removed by update DRC
" {$ y6 u" z! {& V748865 CONSTRAINT_MGR OTHER Allegro 16.3 slow to move component with CM open1 R/ u, _$ Z- _3 X
749009 APD WIREBOND a part of function of the finger alinement doesn't work
2 K5 }8 {' B- x2 _749162 SIG_EXPLORER INTERACTIV Unable to proceed after RMB > Preference > Cancel3 h5 p$ l6 [- l6 ^
749307 ALLEGRO_EDITOR MENTOR mbs2brd fails with error VIF_Allegro_Write3 [- I9 m0 j- L% t; R( E* L, R
749435 CIS DESIGN_VARIANT Cannot create variant part in 16.32 Y- G+ p8 V8 l* e
749854 APD PADSTACK_EDITOR The value of user-defined mask layer is not retained in the design.
' \ q8 H$ ~) u* t$ u4 X8 B1 ]9 L+ Y749891 ALLEGRO_EDITOR PARTITION Unable to delete existing partitions
/ s: N2 r% {- w* l749949 SIG_EXPLORER EXTRACTTOP A Topology extraction fails using APD and SiP series with the latest hotfix(SPB16.30.001).
3 x$ R! E. X7 |% n' g6 {750008 CAPTURE NETLIST_ALLEGRO Netlist different in SPB 16.3 and after installing SPB 16.3 hotfix 1
; u/ C e) N$ t/ T3 b1 o750591 ALLEGRO_EDITOR DATABASE Analyze diff pair object fails to display uncopled lenght values.4 M% A6 `& g3 d" H, `
750888 SPECCTRA ROUTE specctra is crashing while routing. }2 v N& r! l
751204 F2B DESIGNVARI Design difference crashes while reading funcview
% K! G6 i4 q- K/ v* y0 D/ X751398 ALLEGRO_EDITOR OTHER Allegro Crash when Edit is selected in Setup > Outline > Room outline
0 G. |9 G, V; C6 r751578 ALLEGRO_EDITOR PADS_IN pads_in hangs while conversion0 }( |) S4 P/ P- P0 b t
DATE: 02-09-2010 HOTFIX VERSION: 002/ d/ v6 X5 r; I0 }- |
===================================================================================================================================
' G n& g; s5 T- pCCRID PRODUCT PRODUCTLEVEL2 TITLE9 B" ~( c: N! ^ ~" U
===================================================================================================================================
~* C* V, X2 I/ F' A! m- |3 G2 x527012 SIG_INTEGRITY IRDROP Severe Memory leak in IRDrop! k: _* g1 t/ i
623678 PCB_LIBRARIAN CORE PDV freezes when changing grid
( ^1 m: K7 C/ b/ Q. X8 m672592 ALLEGRO_EDITOR SHAPE Shape does not void correctly untill a clearance oversize value is added
) ^4 y4 M( Z$ j" t9 O3 Z3 ^688062 PCB_LIBRARIAN CORE PDV Strange characters appear when copying text into Bus Arrows ( Text symbols) |& o# Q- h% B4 q4 b3 @
710170 SIG_INTEGRITY IRDROP Run IR Drop even if all components on the net are not placed.9 }' ]6 l/ E5 v# {" ^
710174 SIG_INTEGRITY IRDROP Audit function for IR Drop.
p! V2 c0 _ q! j726833 PSPICE DEHDL Modify the methodology for migrating 15.7 and 16.2 users of ConceptPSpice% I+ a6 t2 ]9 J& P# u& C/ E
730717 SCM UI Unable to delete a zero connection signal in SLP which has a pull-up
1 P1 C6 |0 U. [1 p$ D731017 ALLEGRO_EDITOR DRC_CONSTR DRC's show out of date when artwork is run* R& L9 e$ I: m+ |
732145 CONCEPT_HDL OTHER Incorrectly generated VHDL netlist( v$ N$ p V8 j( ~6 S
740123 ALLEGRO_EDITOR GRAPHICS Capture Image command fillin missing from jrl and script files: t' g2 o2 t+ g0 A% B; V
740278 ALLEGRO_EDITOR OTHER Jumper fucntion for Single Side PCB Design
3 g0 U$ @7 Q- P; A# \2 K) W, R740656 ALLEGRO_EDITOR GRAPHICS Can we place custdatatips.cdt file on a site level for SPB16.3( z, P1 u0 b& _
741222 CONCEPT_HDL CORE Replace command (in Windows mode) causes crash
0 Y9 v4 f4 j5 A( g l0 b, J742389 ALLEGRO_EDITOR EDIT_ETCH Change or add message when using Countour route
* E$ c# H7 k3 {0 |743275 APD DATABASE With DRC enabled, this design seg faults in axldbid.c (solaris only). DRC update takes orders of magnitude longer on sun
`# X! e: l( ]0 ~$ s743623 F2B PACKAGERXL Pxl error when using pack_ignore on reuse blocks
- Q# `4 E9 n7 ]. v) A- ~744348 F2B BOM PART_NAME column getting word wrapped inspite of sufficient space in the HTML BOM report.
: E9 c7 o0 H. Q) J745062 CONSTRAINT_MGR OTHER import techfile does not add new layers in cross section t6 _1 j; C/ s9 K" Q
745148 ALLEGRO_EDITOR GRAPHICS Allegro ptf driven HEIGHT value not pushed into 3D Viewer
0 O& Y0 a4 _+ m6 a745301 ALLEGRO_EDITOR DATABASE Allegro 16.3 crsh on moving component Q1 t" q( m" h `6 K( c/ V
745518 ALLEGRO_EDITOR DRC_CONSTR DRCs not shown when "Enable Antipads as Route keepout is checked in"
1 h. z V1 L+ L+ C5 B, b745745 SIP_LAYOUT WIZARDS Die Text In changing the pin names on duplicates
- k* O. i6 _* P f) n! v# r745785 CONSTRAINT_MGR UI_FORMS Unnecessary window opens when the cell in PCSet By layer worksheet was clicked.5 p0 ]2 K' {. A9 l; [% h
746002 CONCEPT_HDL CREFER Could not find pc.db in the root design0 j5 d: x' U' I
746010 CONSTRAINT_MGR SCHEM_FTB Updating the brd file using the "Import Changes Only" option overwrites the modified constraints in
% D5 ^8 f; X- K2 L" X% b746080 CONSTRAINT_MGR OTHER Click Constraint Manager filter icons crash software
1 |0 h2 d# Q) b( a# F/ {# a746137 APD IMPORT_DATA Import > NA2 not transalating certain layers and padstack sizes; d: ]! P+ q6 {6 Y" Q' j0 R6 N
746370 ALLEGRO_EDITOR GRAPHICS Setting infinite_cursor_bug_nt variable flips mouse movement on flip design
8 h! ~2 N9 h! }* T- R* c5 a& s746519 CONCEPT_HDL CHECKPLUS CheckPlus the if statement is not seeing the True condition or the output predicate is not returning the True condition." i4 J" \. m, w3 E1 d
746546 PCB_LIBRARIAN VERIFICATION con2con choosing incorrect PART_NAME in PTF File during verification
3 M2 B/ a, z( A/ n& ~746865 CONCEPT_HDL CORE Tool generated pspice net names in core concept design cause short with copy all.
1 B# |- ` d4 u( t747636 SIP_RF OTHER RFSIP Layout RF Module Export chips & connectivity is not writing die attach method to chips file
0 X6 K6 u# e1 f; u: _2 P6 xDATE: 01-31-2010 HOTFIX VERSION: 001
5 Q: w6 G" I. u" J j% E( _===================================================================================================================================, k0 l! I2 |4 B7 |/ |3 `
CCRID PRODUCT PRODUCTLEVEL2 TITLE% S9 c: n/ E2 Q& Y( r
===================================================================================================================================1 J @. z4 u" Y4 p! ]% j: J
491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute
2 ^ W% F2 g3 _4 D& ~% Q: h# n496910 CAPTURE NETLIST_ALLEGRO Inconsistent netlist creation
5 P, W/ s( b+ i$ e# [558783 PSPICE NETLISTER Why do Models with "awb*" prefix need wirte permissions to "*.ind" files?
' _; W5 { ]* ^7 o6 m% Y( w643241 CAPTURE SCHEMATIC_EDITOR OrCAD crashed while replacing cache
9 k! a9 {# ]/ ?# @: f& F654292 ALLEGRO_EDITOR DATABASE Propagation Delay constraint behaves differently between 16.01 and 16.23 F1 [* u# t' O- r1 @& a
662829 CONCEPT_HDL GLOBALCHANGE Global Update should honor property visibility settings in ppt_optionset+ k/ c% j$ V }, f l$ ]3 M
672718 SIP_LAYOUT EXPORT_DATA "Export>Symbol Spreadsheet" should export a .cvf not a .txt
: I$ z# S% v& w- i7 \( _! B. U5 d# S676233 CAPTURE NETLIST_ALLEGRO Cross probing stops working if design name has dots! i# d/ K z" }
678739 CONCEPT_HDL CONSTRAINT_MGR Manually added targets in matchgroups lost when reopen CM
5 U. \( ~! h- c2 k690618 F2B BOM Write protected template.bom fails to write callouts: V, z1 l! _; h5 \5 F- U3 q
700246 CIS LINK_DATABASE_PA Need option to update symbol always when linking part in CIS
% f, D% I- r$ u+ f4 v705393 CONCEPT_HDL CORE ConceptHDL crashes while switching to another hierarchy level under File > Plot Preview.
' q4 J0 D; s" K+ l( `) H: R9 M708634 ALLEGRO_EDITOR SHAPE Shapes getting incorrectly displayed in 16.26 o4 i' e$ b7 |
708950 CONCEPT_HDL CORE Tool crashes while trying to change the text on the schematic using a text editor.
* i/ K2 i- j2 g2 [8 [& v' L709823 ALLEGRO_EDITOR OTHER Arcs not converted properly when upgrading symbols4 _' ?+ Q0 D( d# M1 F
713964 F2B PACKAGERXL Net property Probe_Number is getting changed during the packaging run
9 g! j! K5 B# ]4 H3 M9 J718119 F2B BOM Exclude the callout file name from the template.bom file
1 j7 ]: Y t6 Y718496 SIG_INTEGRITY SIGWAVE Frequency at smith chart.! d8 V5 g5 ]1 J" N
721422 CONCEPT_HDL CHECKPLUS Checkplus fails if "\\" character is used in the parameter list7 h' [8 x5 a. r3 U$ I4 `
721788 SCM OTHER SCM unresponsive while closing out a Block without Saving; |8 u+ x* Q- |+ ~
721801 CONCEPT_HDL CORE Save As crashes DE HDL if an existing page is selected in the design+ @& {; q, J& q( Q- R! P' V* Q
722653 F2B PACKAGERXL Packaging does not complete& Z7 Q8 \* S' [$ s, |3 {9 D
725285 CONCEPT_HDL CORE nconcepthdl does not work same as concepthdl for same script.8 N* j- ~3 B: l* z$ b% q. S
725719 CONCEPT_HDL CORE wire pettern of Publish PDF
! E0 ~% z5 X" u( M5 Q727062 CONCEPT_HDL CREFER Custom properties not visible for TOC symbol in schref_1 view9 n6 }) s5 q7 a4 |3 ~& ~
727194 CAPTURE CORRUPT_DESIGN Random Capture crash
$ _- j4 B+ v, I727704 SCM PACKAGER ASA to PCB getting out of sync' ~8 Y, U; S6 ? a. J% b; `+ E
728066 CAPTURE NETLIST_ALLEGRO Allegro PCB Edtior net cannot be generated if PACK_SHORT is used
" c6 Z7 w& P" ~3 B729214 CONCEPT_HDL CORE SHOW_PNN_SIGNAME directive used with Windows Mode gives crash
1 y" F$ m4 h. H& s c730295 SIG_INTEGRITY OTHER Filled rectangle shapes not extracted properly% A3 v3 Y" V/ |9 F- ]* m1 r3 P9 h
731183 CIS QUERY_DATABASE CIS Query fails with ODBC Error for query (Price contains 29)
) V3 Y |1 K3 L2 d& c4 p4 Q- k* s732073 SIP_LAYOUT DXF_IF DXF_OUT generate an incorrect shape
1 {% I# e' D7 F6 i6 b" j732138 CONCEPT_HDL CORE Cannot change SI model assignments
* w( O- I U) t( t732216 ADW DBEDITOR dbeditor crashes doing copy-as-new into lib folder that has partially completed chips.prt file3 r1 j8 ^0 _4 ^, L( Z1 C
732249 SIG_INTEGRITY SIMULATION Probe sim with custom stimulus cause segmentation fault. Linux only.
/ |8 P" @- _ N2 k, A# \; ~732847 ALLEGRO_EDITOR DRC_CONSTR Manual Void uses Shape to Pin constraint to void Holes9 l! u0 o8 H: O! I" W
733261 FLOWS PROJMGR Project manager does not work with the Restricted User in client server environment
4 `) g, \+ O9 R9 S: j733773 CONCEPT_HDL OTHER Syntax issues in DEHDL+ e# A F6 V; B
734260 APD COLOR Why subclasses still remain visible even after global visibility is turned off.
! v# v. x( D9 R$ [1 Z734419 CONCEPT_HDL CORE Concept crashes in windows mode when netname is deleted on schematics generated by ASA5 |) p y/ E" t, P. O- h- a- g
734555 CONSTRAINT_MGR SCHEM_FTB Import Logic does not overwrite the Constraints
. i4 G6 h \; d/ {1 b735290 CONCEPT_HDL OTHER Concept's PDF Publisher has issues.
3 i$ Y* t2 X+ i4 ?2 w( o735892 CONCEPT_HDL CORE "Component Modify" changes visiblilty of Key properties$ w3 v) y3 m ]$ P
735977 ALLEGRO_EDITOR MENTOR Mentor to Allegro translation fails without any error message
' s# J& M6 X9 v( u" ~736071 CONCEPT_HDL CORE Property visibility is not retained on the schematic instance when we modify the component on sch.4 `6 j2 b7 K, {" t( G
736165 SIP_LAYOUT SCHEMATIC_FTB about error message of "schematic to layout"/ f( g8 {0 r& {4 }. W* u( L
736167 CONCEPT_HDL CORE HDL crashes when I select BGA symbol in Component Browser
4 I5 C* R! x1 U; n1 z736911 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge
. [ u( j/ o, Z$ g738035 ALLEGRO_EDITOR OTHER Measure function has different result between 15.7 and 16.2 version./ ^! i0 o! `4 V7 X3 j
738129 CONSTRAINT_MGR UI_FORMS Need Diffpair Constraints option in Analysis Modes Electrical Options with Performance license0 t/ @* I% c* h" Q3 Z& q" M4 R
738276 ALLEGRO_EDITOR PLACEMENT No feedback in console window when placing unfound components in Allgero 16.3( D" X) A9 L5 s* G3 {' S8 z' T
738366 ALLEGRO_EDITOR GRAPHICS 3d viewer not showing some connectors with mutliple place bounds correctly. D8 r) V1 P. p( ~5 o
738454 SIG_INTEGRITY FIELD_SOLVERS EMS2D extracts incorrect CPW to Trace spacing
+ y' E" m5 ~" P, G* }9 Y# D! H! n738578 ALLEGRO_EDITOR OTHER scriptmode +w doesnot work on Linux: z* H* C# M6 I6 e' k: C' o5 U2 s
738869 ALLEGRO_EDITOR OTHER Error msg when cds.lib contains missing SOFTINCLUDE
$ {1 G* U9 r9 d) {739116 EMI SIMULATION At EMI simulation on SigXP an extra Sigwave form is launched.
$ P: c+ b- ^" t4 _" M' |' g3 d. ~739225 ALLEGRO_EDITOR GRAPHICS Ability to lock the 'Hide Pallette' option/ E. h2 R9 Z' W/ S
739599 ALLEGRO_EDITOR DRC_CONSTR drc_errchk indic4 q; j! O" M; N7 c- z* V) M
739628 ALLEGRO_EDITOR SYMBOL Opening a symbol file is crashing allegro.: p" ]7 ]4 H( s6 `3 @8 J+ j
739653 ALLEGRO_EDITOR SHAPE Shape created in 15.X .dra changes geometry when uprev'd to 16.X7 l; a( C/ _# t0 i; V
739661 ALLEGRO_EDITOR OTHER Export netlist creates incorrect via_list syntax.
0 r% y6 M. @: \- }739872 ALLEGRO_EDITOR SKILL Crash while performing axlExtractToFile in 16.3' o6 v; _% [- {
739934 SIG_INTEGRITY OTHER specctraquest crash on changing signal model; B0 a3 E) M8 s# ^ S
739937 MODEL_INTEGRIT PARSE zero valued estimated parasitics in ibis models7 L7 W3 B6 e/ c, o' j% ?, ~
739942 ALLEGRO_EDITOR SHAPE zcopy xhatch shape creates oversize copy
9 `* k5 j2 ^+ T740133 ALLEGRO_EDITOR DRC_CONSTR Same net DRC Update from Analysis Modes runs forever.
, E2 E4 e! G+ ^2 h. E6 A8 W740281 ALLEGRO_EDITOR OTHER Jumper components where were placed in PCB disappeared8 B4 Y! W0 v$ J6 s2 s& i0 z# B1 K, e3 D
740309 SIP_LAYOUT DIE_EDITOR Moving a die pad in DIE EDITOR on G69A_U1 causes the die pads to rotate 90 degrees from the design.
" ?' s3 m4 k6 W" x4 R6 ~: V$ h y740399 ALLEGRO_EDITOR COLOR Cannot automatically load custom color palette in 16.2. K( n9 W4 Z& {& O" A' R; n+ H
741210 ALLEGRO_EDITOR DATABASE Edit >Move; spin creates 'connect record not found' message
1 ?! j$ v5 T1 q6 R# D741307 ALLEGRO_EDITOR PADS_IN Shapes on some layers is not getting translated from PADS into Allegro
6 Y1 W# u' M7 t- _741313 ALLEGRO_EDITOR DRC_CONSTR Add connect slow in 16.3
7 p" @5 X( m) `/ p6 C$ a5 d& u741778 ALLEGRO_EDITOR COLOR Color pallete in 16.3 is not expanding when maximize dialog' [& u0 s1 F- x8 C2 q" p; ?* U( V
741910 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd! u& x+ T) I6 S6 [9 ~
741939 ALLEGRO_EDITOR PADS_IN PADS to Allegro Translation fails or hangs., I" l! e8 N7 e {. y
741980 ALLEGRO_EDITOR PARTITION Import of parition does not import etch or vias.+ I0 v, K8 L* `# r/ J6 b( x) n
742676 ALLEGRO_EDITOR SKILL Tpoint cannot be moved by using skill.+ E3 ^ J. a. H' Y
743161 ALLEGRO_EDITOR SCHEM_FTB Netrev crashing when importing netlist into board file.
: I5 g8 N3 m5 _% F! |743235 ALLEGRO_EDITOR PLACEMENT Allegro crashes when unmatching comp in placement replicate.0 }6 K2 e7 E8 w$ D+ u! k' ?" ^
743243 CONSTRAINT_MGR TECHFILE Closing CM destroys tcf values when they are set to locked using fObjectNOTReadOnly
4 k, d7 _' n/ \: t$ _743301 SIP_LAYOUT DIE_EDITOR Edit die command creates two extra die pads- I* s. L, a# `% A4 h3 C
743316 CONSTRAINT_MGR DATABASE With Allegro 16.3 Constraint manager takes to long to update
& ?9 R+ a$ m& Z743553 CONSTRAINT_MGR OTHER Net disappears if we cancel the line width edits in CM |
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发表于 2010-6-3 12:25
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