|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
===============================================
* `* K7 I! Q; {! R* l- @3 I. H8 x2 A* V) {& q( C. I
CADENCE SPB RELEASE 16.3 README -- UNIX Version
' a- ^6 ?% P4 A# p+ y( z7 K! t) g; U/ {
===============================================
9 J) u: Z+ `1 i) K
) p4 k( M: [' y* |1 i( Y+ b3 ?4 k2 H0 c( w7 O5 A
INSTALLATION GUIDE4 A! q3 ?, C- t/ j3 {6 w; b
5 R$ p1 S# L# I+ w2 p
--------------------
* w' f8 S3 K9 N' C m, |You can find the UNIX installation guide on Cadence Online Support or the' u- u8 s, @+ a& j9 e( c; s
Cadence downloads site.0 d' }5 I8 p1 B3 F' @
" Y: f& p4 B" A, M7 K( x7 r
" x4 B. ]+ Z" G" r# ?; w8 ?2 b
MIGRATION INFORMATION4 V' w+ M* j; P! H' O& {
- f/ z+ M0 |+ ]; K) x: [( D6 v
-----------------------
4 j- a$ `, h( bImportant migration information is contained in the "Migration " I6 G* n+ R5 c+ C! D
Guide for Allegro Platform Products Release 16.3", which is ' T) R' l" }2 \ v$ L& v
available when you install this software or on Cadence Online Support.
3 x" h* }' p6 {5 j; u, w( V5 K' S& n* A, j9 l
" p5 z! {( c. Z6 q" v4 h8 hSYSTEM REQUIREMENTS& s( ]: A8 z5 g* I! j# a
: D4 P" O( [0 h3 O----------------------* w( h: _- p5 d
7 h+ @& H" H0 X
Information about minimum and recommended system requirements can be ' A5 ~/ Z: ~: W( D' G6 R
found in the "Allegro Platform System Requirements" document in the ( S3 }) b/ v$ o( R! ]
Cadence product documentation or on Cadence Online Support.$ n9 ?/ z" }6 ]4 F
2 m' U5 C" E' w2 O2 q
1 x8 d* n' |" F4 ]
WHAT'S NEW
% }5 X: Q, t9 O2 @4 j2 ?----------
9 x6 u5 P! K5 U" d" LProduct release notes are available at:
( F* y* V7 e" P% h5 l[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin ocumentViewer]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer[/url];/ z: w) }! f, b5 D* {
src=pubs;q=landing/spb163/prodList.html
5 [+ T* l# r/ x: b+ z$ g6 l: J3 l+ C, W
j' Y! s2 A$ B7 Z2 e
+ b) ^( M# J; ?4 j4 s/ LKPNS* _, a4 H+ @; s7 s" a* S
----' i, u" R& P# E1 Y$ U0 l
The Known Problems and Solutions (KPNS) document is located at:
+ U2 ^- t% k: t: [: N* }[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer[/url];; ^7 G4 {- {/ l
src=pubs;q=landing/spb163/kpnsList.html d( F5 e1 h4 h' m6 P
6 x' r6 `8 j/ O' g( [2 S* Z% j! a" b* F# s
Allegro /SigXplorer ABIML LIBRARIES FOR DEFAULT TRACE MODELS! b3 |- H! Z( e
9 g2 Z- k6 X# ^9 \
--------------------------------------------------------------9 n, U1 u4 T/ E/ M9 u- J% {: G& ~
The Allegro /SigXplorer ABIML Library is a free library that includes ABIML
+ F8 Y, Z5 I. Y% mlibraries for SigXplorer default trace models with surface roughness effect. 2 G3 w/ b& e% @* l) L
It is designed to provide accurate trace models in Allegro /SigXplorer without
7 l* d# i: D0 h6 r9 p7 Y4 A. Dtime consuming EMS2D solver runs. The libraries can be found at:! k& t. ^1 l+ c/ t0 X' l3 a Y
http://www.cadence.com/products/pcb/pages/Downloads.aspx2 g, \9 ^# K; n& N- t: n
7 j* u4 c2 M8 L; N( `
This ABIML library is provided free of charge for use with Allegro and SigXplorer. ; I4 b7 |7 b& X) P
The library is provided as a zipped archive, with installation instructions included.& s$ d4 L8 l0 q6 U* o; H* Z, y+ @
5 X2 P+ D7 _ |
CUSTOM ENVIRONMENTS# U. d! z" m6 ?
( ^- W* J4 e$ G% F1 z6 R-------------------3 x- u3 o& X6 F! h4 S
Customers using custom batch files or scripts to set up their environments must add 7 V9 D s3 u# s+ w; a
the following to their path. There is the potential that some Allegro products may not% W; V' s& C' U( n, q, N9 ^
launch without this setting." o {" M( O1 g" \# ~
%CDSROOT%\OpenAccess\bin\win32\opt
7 S+ l/ l# q0 a% I+ ]
5 @9 i$ e& c }: ]! {# |) N V3 `
4 l7 J7 E+ u" D( u; s6 u% @2 N/ _
( j8 n2 O- L! r4 T- p8 s4 E7 d6 W
List of Fixed CCRs
9 u9 u2 Z. B5 H1 V7 v* @-------------------
5 e8 x' @. [6 g1 E% s2 |-------------------
+ N( O4 R" R3 t( x, |& _
6 @: N2 ^, a& {: B8 m( @+ {; \
9 U: ]- T( F5 @7 O1 ]ENHANCEMENT CCRs
$ l+ T$ _& e5 M) i+ O----------------% { |" G( s, F# N! f, k8 |/ q8 D
) s! ?$ w* ^2 v( x C& B) y
CCR Description
: j% }4 J3 [' i: X----- ----------- + d5 p+ Y: n( c: }0 g7 f
----- -----------
8 B% ?. I3 b1 H3 @0 u# K% V5 K# ]9 s( O) V D9 {/ |* ~- V5 W8 J1 s* @
7419 Customer menu options added to Allegro menus3 d- z! e- R6 s7 u. `! F
8230 Use via in area constraint does not work
0 ^% G) j4 f9 ^2 ?/ @10658 Modify default formatting for Label texts and linewidths, c' B8 q7 p) k8 f0 ^" s2 e3 y
12216 Cannot set color or line width for wires on net-by net basis
3 A0 W- m( m. |$ h* Q# u13083 flip/mirror design to back side
4 P3 H/ k) n$ Z \& r13373 Select length of pin graphics
0 J9 h3 q4 v$ J" M+ [& \; C18072 Add docking option for probe cursor box.& w# A7 H3 Y2 \, Y& L
21451 Change Probe print trace color yellow to alternate.+ g! O2 P8 U5 W- j# t% I
32798 pxllite complex hierarchy netname enhancement
: Z: P- b4 f) U0 _/ `39600 Option to see time spent on allegro database
1 h5 p s, q$ |+ \60427 Add different subclasses for pin_number top and bottom
# [; w- d* [7 V' }4 {$ s132769 Footprint viewer in CIS should also show pad spacing info6 l2 {/ V9 p9 | C" f" _
158838 Need easy way to delete marker
; _) D+ R$ C/ @ G# n, L7 {' \ M159977 need attribute mapping capability in mbs2lib and mbs2brd. [& L4 l1 b/ O
164790 Improve autorouting quality on diff pair w/match length rule
9 [5 o8 D T; E' D205909 Constraint Manager displays in Allegro no graphic mode) [7 V$ \# y- K* j
210027 Delete dynamic shape removes net name from copied vias
: J# l/ W4 B% D' n222127 PADS_IN: Constraints are not imported with the design.% x1 Q/ |6 `& x) u/ \( d
236698 Report Unused parts in multiple parts package should be DRC
# i( t5 V' x, z; A# w4 S245193 export dxf height information when blocks are unchecked: i% g- C$ G9 U1 H
254183 Multithreading for DRC and CM analysis in Allegro
5 l. F, i: W8 [% [2 @282027 Problem with Split Part and part graphics
, l; x) D! I$ @0 h" K! k282507 request to import IBIS file directly
+ R7 N7 b; Y; L7 r, t$ |% g, y283698 place by schematic page number window need enhancement5 L [1 t; q8 P2 A0 B% }
288540 Schematic page# display order request for Quick place
; N+ o2 o+ a4 b0 _& ~0 p290641 Option to copy paste cursor value$ |# B8 w# U8 s+ @0 [* h
298081 Models from Funtion.olb need more explanation
5 R3 M$ I" n1 I* P9 R$ m& c& W323813 Need negation and exclusion function in ADE reports8 j. l$ t; T# H
341484 Wirebond: Tools to generate wirebond manufacturing outputs+ p8 @3 p$ z( e5 \6 G/ a3 b# S
353212 Variant Name is not coming in Standard BOM
& r3 z6 f4 L/ w0 n8 K360602 Enhancement to Show element on a via0 S8 P; }. Q% i1 ]# a$ B" R
362934 Enhancement for Allegro to utilize Dual Processors.
( r# {4 @% Y( m# N* p/ i/ s7 n, v364850 change the font properties of Label Text/ X4 W0 S/ l, P
367468 Need a real DML_PATH environment variable' t) X) M4 h, b9 F2 F
380714 Ability to have Power pin set to Not Connect
3 p/ J/ c0 D/ F382860 Display parts and nets in different colors
" H' ]$ F* o/ W384488 Add DEVICE and REFDES filter to Signal Model Browser1 g9 }$ x2 \3 ^( x, j
391487 Ability to have user defined directory for storing distribution files for MC analysis4 J! b, C3 r4 B; Z/ w' X$ A( B
420008 The renamed differential pair names are different in CM of ConceptHDL and CM of Allegro., ?2 ~5 r4 L( `* Y2 l
420023 It should be possible to Delete a differential pair defined by SIGNAL_MODEL (.dml) on CM.
: T; `: L3 Q q7 ?$ q420648 Need to get RF Elements to retain previously entered values
# T- ^& e! q4 S$ U6 z429280 ARC is unable to load/save rules - submitted for tracking with Medtronic SiP benchmark) ~$ w* J7 K$ D! `0 N
430549 GUI for ADRC XML Rule files
# c! t7 j# z v" k430558 Store last used ADRC rule check ini and check values in .sip database
t4 A/ u# _% b6 s ~452606 Can we have last plot as a default ; R" ], Z! f4 O' Q$ y
454452 Allow neighboring/overlapping die pads on same net to go to same finger during wirebond add.
- U: k$ \9 H8 `0 R7 G$ Y464056 Setup option to always prompt to baseline a new part
5 c* m5 X! g" Z% r8 ^ s469378 Enhancement : Hide/Unhide feature for trace
, K$ }. I8 N: p475077 Schematic Generation Setup form is missing the Port symbol selection. It was there in the 15.7 release.
/ X7 h4 P0 H6 G4 ]; Q5 E. ^: b475714 User Guide should mention that Temp Sweep is not honored in AA Flow?
9 `/ i& g* q; F6 i. o. L0 ?4 n480843 Requesting ability to View > Zoom Mirror current view.
0 S+ h" i# Z5 X1 N484632 Request for Bond finger to snap to Guide in Free placement of Bond pads% s, p9 C8 [- V: \! f" T
490948 Provide a sketch line and text property form
6 K# [/ c9 U& f1 B4 m500550 CRef's should be preserved with the next run of the schgen in the preserve mode.( h X) ]/ S, ], Q; m: P; Z
505284 Enhance The ConceptHDL can set the color for $XR0 property.
1 G" B6 S1 U, z/ h512748 improving arc routing6 L( W/ M- X/ d& ?5 H% a
513967 staggered C-line via arrays# g/ H: z. ?0 X: c/ @$ u! E
515333 Option to specify spacing between Components in the Generated Schematic) D+ e0 ]! b, U( t( c( d$ o! W
525748 Why is MC Analysis Sigma value 1/3rd of 15.7 version value?+ R8 T8 d7 [$ O0 o O: i
526818 Retain Hard Packaging Information option does not work for SECs.( `3 b' h6 Y8 e0 k. y. v# u. m
528391 SigXplorer measurement is wrong% X9 p, ~" V+ ^+ W6 `
533844 Allegro password not encrypted in the .brd file.
8 X( K1 @7 d( v6 {! U536681 In the ADRC tool requesting a "Layer" option for Conductor to Package Substrate Edge Spacing7 p3 R( u2 M1 [8 A6 P! i
536948 Allow sorting of power symbols
) P- t7 e% h5 \1 s539407 In ADRC Minimum Shape Check requesting individual "Layer" option
6 P; c% J/ D3 m/ J9 i541145 slide command does not support to keeping the existing arc
/ R% T; A f' I1 o( e7 v& w541214 about supporting OpenDrain Model in Quad2signoise
- B6 ~, k5 d( U( F542414 A function to force diff pair spacing to primary gap.9 A' h4 G7 K# e. X. j
542803 A "Minimum Shape Check Soldermask" entry is needed in ADRC
" n% |- R8 ^( v/ g! T543470 Provide rectangle and line width thickness for Drill legend in NC drill Param
; v5 A& G5 M! W" v0 ?+ m543766 Crefer fails to annotate occurrence properties to offpage symbols in replicated blocks" ]7 O$ x- U+ C
545408 Cursors are toggled off when deleting a plot8 w8 }" f4 W+ B6 C( s( W
546891 Enhancement: message improvement when expand design action in Concept
% i$ M8 A8 I5 m9 Z# P. X/ Z546985 XOR function to allow to compare layers within different or same designs* p! S, J4 o1 f+ y4 `4 t/ q
548920 Add a document of which properties can be synced and which cannot be and the files required
l3 ^) \! z+ g. k/ p553669 Add a 3D viewer to Allegro
) j$ y# P% _% Q; j& a2 J$ b555183 Wire Bond Report --- Report field should have save function for reuse" z+ V! k: p: s4 ~
556200 Need listing of DE HDL command names and switches.
: D5 K1 B. R) p9 a/ N0 x$ Y7 U2 Z556883 Grid point for Origin to be highlighted( x% [' ^1 h5 A- t V4 Z% z2 X
559638 Enhancement for importing height from PADS in allegro+ P- h3 {7 e" `7 `. L) k3 S
559724 Request cline via arrays to be applied to diffpair nets0 b$ a: c- M' L7 e3 F
560134 Show Element Customized Display
1 Y3 M! S! i A# _563957 Enhance Color Dialog form Class/Subclass section to expand vertically when the form size increases.
A" b. t. W! {) ?- a7 o568058 Request to have component information available through the context menus
1 n" E/ \* @9 ]569615 Enhancement to import constraints from Mentor Board Station to Allegro PCB
) L+ U) W- @% P0 p569680 BOMHDL defaults to the wrong file type when html report type is selected
3 v9 [3 z% U- r2 S/ M569784 Request ability to assign netname to via during copy
3 h. p: ?: T/ j569863 User would like to set a larger default trace width
3 e& H, O7 X v& Q* z3 |$ U570128 Enhancement : Packager setup for subdesign drop down0 |' {- U/ I2 c, F4 N; U0 X
570195 SiP - Provide option to create/combine BF labeling with additional text required for Bond diagrams
) Z$ b6 ^7 t3 U' d- V1 `570861 Unconnected mark does not be removed even after wire is connected to the pin.
1 [7 a- ~/ ] {9 R575211 Web links in CIS explorer are not working when Firefox 3 as a default Browser4 [- O r# B- M# {3 `9 o. ^
577944 Enhancement request to have the drill legend for thru holes and slots to be separated without being on top of each other
2 O. B$ { Y! o0 K583630 Can Multiple Section pop up box be disabled?$ W9 g2 X$ a+ I' O$ b
583712 Ability to have string values for SCHEMATIC_GROUP property
3 G9 p8 g& k/ k4 ^ H- e585904 Find a schematic page with help of nets0 R4 @% ~2 F1 E, y' V7 E
589512 RF component snap is 'too clever') _; M/ X% u# P7 r
590246 CIS to Allegro flow to include or ignore constraints same as HDL to Allegro: U+ f' o% f# S5 ^0 s, A, Q5 h
591306 Suppress RF edit window when changing RF Element properties/ } }. m6 O) X1 e5 W7 o, d, _
591318 Use RF setup values or retain changed values in RF Element forms
$ Q/ ~: @- Y F7 E" X591443 Temporary highlighting is lost when using the Copy command
7 A5 H7 P9 H0 i+ v591450 Provide a dynamic tapering option to RF PCB Route
& L( y# k! V2 F, O: T: j591489 Would like to suppress RF Snap windowing around the user pick automatically# ?8 ]( o) W7 X, P! F
591812 Provide move options for the RF Snap command' T/ K8 O1 d7 q: f
591817 Provide easy group and element ID in repackage form' G1 k- U7 Z+ p- F5 v
591825 Quickplace for RF Elements
8 Z0 F A4 q# X c' t! F9 f591865 Request for more information on 'Other' Netlist formats
3 \# o3 ?, C8 z) Z( _596392 Publish PDF needs improved error messages for missing installation.0 T$ S; m \: p3 E. F! ~1 s8 G5 l
596555 Request alias symbols documentation to include and clarify when necessary to rotate 180 degrees
7 m) B1 C. O U7 V I5 J# e596843 Cannot do global search after importing read-only schematic block
% t! U h7 s3 f) ^. k. _597808 Option to increase the default thickness of all traces in Probe
+ I6 V- v- A" F599499 Plotting from within Allegro does not find path to stipple file
0 y4 K! i& w( N" r, B604125 Manufacture>Create Bond finger Soldermask.2 r. B0 [3 S( I3 J' `0 j
605023 Need rats by layer function for Free Viewer
* U& C$ x9 A7 r* n8 a605112 Dies should not be counted as conductor layers in Design Summary Report of SiP( F* v- _: v. g, c
605373 importing and Exporting BondWires# T: @; _6 ~- _
609035 Voltage_bus part - Make pin number invisible8 q1 `8 i9 Z" `4 J8 ~0 [0 S
609561 Enhance Circuit Replicate to support coppers shapes connect lines and vias( A1 J3 h! y4 Q& E! n" T8 X
610934 Retain user input values in RF PCB forms
% \( h& i( P0 S* f. l& u: J, u F- ~612008 Mirror Rules need to be documented for axlTransformObject.
- q, s: |3 z+ A$ j; c W1 \613639 Update Documentation for "split_inst_name" property.
0 ]& B% ?, K) [- ]+ o& x614345 Email facility for Design partition on Solaris does not work
) K0 I* a1 A! |. F615139 option DMFACTOR documentation missing in pspcref.pdf( q4 C" c5 Y* k0 @1 N
615374 Retain Soldermask Thickness value in 3D Viewer Options- ~$ V* G7 r( `9 d# a4 q" k
615850 Auto Setup should honor device setup parameters if component value is null
! \( G2 o- z5 a' m3 X w615988 PDV WHen importing from Mentor does the browser not remember the last location of import
- g4 ~" l3 M' D: ^, G& Y/ N616529 15.7 Design Entry HDL fails with Out of Memory message7 a0 T/ b+ Q: b# Z9 A$ b
616873 Uppercase characters in design name error should be improved
: a6 k' l1 n9 Q8 @6 `* S- \& m617976 Enhancement for a way to sort user subclass in define subclass form4 G# P0 l7 g( X L+ N9 o4 s8 H4 C
620289 Server 2003 support information in pcbsystemreqs.pdf
( }4 V2 Z; Y. l5 i620303 Enhancement: Shortcut key for "Select Entire Net"8 A/ p; c7 F2 y ]
621054 Renamed net in netlist isolates components from the rest of the net.. K# N) x* P3 W4 w( i
621955 Offset Via Generator utility should show a warning message if vias are already present.! r/ D v. X1 C
622203 Requesting that "DFA Constraint Spreadsheet" icon be added in Customization >Toolbar commands8 E$ x5 S1 T' w* S
623218 display pin names associated with a net in net Properties
& m8 j* w# r& G- E g623908 Mirror Symbols while dynamically moving enhancement
/ e; l/ o5 O* w& C# Z624817 Display padstack name in data tips when hovering over Pad-stack
! [' F8 q. q5 k9 t4 _625733 In Netlist Report they are requesting square bracket vs angle bracket
6 A$ b+ y, ]* L; Z626605 Extract topology with routed interconnect to include via's in Allegro DesignPlanner, PCB XL and PCB GXL
2 w& A1 ]7 Z# B9 b" e9 E( s5 D: b1 f626673 16.2 Die Stack Editor - Add option for DIE x y cords within DIE STACK form - shows rotation and allows move but7 Y7 E& _9 S- k, _' |# _/ K3 Y/ J
629008 enhancements for find command
9 a! V5 X, G* S+ e629548 Request an Option in Create Plating Bar where it may be directed to a different Subclass
3 h' I( m2 I" n9 D; _( T& Z630949 DRC for bond wire to bond wire requires additional parameter "wire profile" to "wire profile"
# v5 V9 g8 B* a( H630955 SCM does not see design difference after update of fixed die/BGA in cdnsip9 K) {6 D S2 u
630973 SCM should see the net assignment made in CDNSIP for Power and Ground pins0 _" U+ U) @) @
631609 Clarify how to generate a cref.dat file in Cadence Help
/ |* u# e3 B* D8 b& d, l! k631697 Want to degass many shapes in succession with custom parameters8 {" D" c/ }0 Y7 @8 v! o
632754 pspPN and lib_list should reflect location of new models in 16.2& _# b6 X' W; t4 ~. Z4 s
633440 Sensitivity not varying components correctly( F6 i7 Y2 g; x$ Q, w' v
633842 Add note to docs regarding padstack quickview
5 X+ P" ^, N3 J# D8 Q, Q0 J3 h634350 Enhancement suggestions for pop up info boxes.
0 Y X# y$ H3 D( x634877 Export netlist with properties changes scope from global to local$ R u# {; v- z: Z
635118 SKILL variable to obtain list of Classes and user defined subclasses in a database7 l v. Y' q5 r3 V( q/ l
635233 Place hierarchical pin tool tip
' R D6 R0 X1 n, ?635543 Any command to get the current line/lock type information?
[3 h+ h+ n0 F( N) A) z% p635579 Enhancement for Structured format in parameter file/ _2 P3 l7 Q3 N8 [' u2 m
636930 Die Export option to create symbol either from schematic or layout! X/ }4 y9 a% v% T: T
637195 Allow for SKill access to backdrill info on padstacks
) @$ J: s2 Y j O637768 Enhancement to assign different colors to different net based on a unique property& f8 D$ h+ q3 j1 I7 Z
638455 Enhancement: Add some details regarding nomd.lib1 u( x# @1 G4 r7 N
638581 ENH - Press ESC button Spreadsheet window disappear
$ b+ v1 h: `0 `4 ]# j638622 Add note to CM Spacing Domain Region worksheets regarding shape2element clearance( @4 ~! W3 \6 F2 @" w
638910 Enhancement to sort the list of available vias alphabetically in the via list ?
! [/ P; p0 R2 i, n639630 Does the Net_Short property work with Modules?% p* E4 C9 }+ [, e' m- o- S/ R: O. w
640262 Request object membership count in the status line and forms of CM.' r9 [& r$ X# G/ A8 _
640280 Provide resizable windows in CM and other apps
7 \$ o3 O; ]- K8 [ j640668 File>Change Editor needs ability to go from GXL to Performance L or Design L.
4 R& m; @; u& T; V x h642095 Ability to disable the Pop-Up description of elements& {8 t$ I& d7 D6 N9 o G3 r
642298 ENH: For license checkout detailed message
+ P) r! k' L" ~4 v4 x: P642422 After Copy parameters from one part to other in partmanager forgets previously highlighted line
" g" j( M; Q7 \9 q$ ?( v642865 Allow format of hyperlinks in ptf files
# @/ C, Z& {6 u% } ^1 ?/ r642894 ERROR(SPCOCN-1993) is not documented anywhere in Cadence Help$ m0 G$ [% u9 y1 {
643381 Add an option to ts2dml to allow user specified port ordering. I& y9 |4 A1 j# n t3 C
643390 Request for a switch or button that would allow Properties to be maintained during a shape merge
- {$ J" K" F5 H& D% G1 Y) p643625 Bond Wire export to DXF does not support WYSWYG( ^# F7 a* |" P Q1 |* w
643790 Include Associated Components in the Verilog netlist9 v! C6 a6 m; Q7 E( e
644216 Store Filter Row Data and Units Of Measurement in site-specific file.
* G( Q% |5 F: W644248 Need a better solution to identify and handle unstuffed components
$ g+ k) ]6 E0 n" V! a& n- K644350 Incorrect upper/lower case for axlPadstackToDisk in Allegro SKILL reference manual
0 U6 x2 O+ _9 @3 \: Y" @* \646662 Enhancement to add feature to toggle on/off inter communication tool from within PCB Editor when using DE CIS.
* p$ h/ m% @, c" E1 Y; r# h646981 about the treatment of NO_GLOSS property in Missing Fillets Report
& }: ]" J% K) _2 i; [647480 global setting for adrc settings in sip via techfile
, \ t% y4 U# F# h4 `/ r! W647617 Degassing not suppressing shapes less than size specified
0 N" J2 C9 S* E, R# s* z648210 Request for Working Layer (WL) model in all tier Allegro tools..
; z" o* }8 e: ]2 s$ {648218 must delete keyword "multiwire" from Doc
, j0 c# T+ R; l648533 The cross probe highlighting between DEHDL and Allegro PCB Editor is not documented+ @. [- _5 s4 h7 O! k/ |! K
648801 Stream Out issue for SPACER
" M7 T# z8 q9 S `) f# S# o0 {648930 If two PPT option set names match a given component which one will be used?
8 x" \% q/ z& _8 o: |649603 about spara import1 k8 @( q2 l( _" b0 j' ?$ e, g
649607 Management of SiP Technology File and Project Information3 n+ O" p; r- {
649610 Management of Part Table (PTF) Files' Q- {4 W' s; ^2 S9 A4 V
649613 Management of Library Lists
0 |/ u# x) J F" t; U' V5 y652335 Tooltips clutter Place Part dialog.Option to switch it OF and ON0 k! h* Z0 Q" t
652511 Unplace Component command. V; a3 L/ C: h2 R3 y
652554 Enhancement request for Allegro to check the vias used to the allowable vias defined in constraint manager! T9 f* N/ W# ~% Z4 |; B
652939 Is there a way to predefine the values for Sample Start Height and Sample Start Length in Wire Profile Editor?
; ]0 `% Q" g% u0 T( L" g1 A653027 Explicit RMB "Done" option is required in Part Developer symbol editor when editing text& O3 o6 f, L9 N7 Y0 J- o; h
653359 Setting the $PN to # does not set the pin numbers to invisible when part is sectioned using the section command, A" }+ [: V$ @
653420 Enhance ADRC rule for Acute Angle Merged Metal Check to work on a user defined minimum constraint value$ L" D8 \, A! X) Z+ q/ M
653471 Request for Die Text In Wizard option to Flip the DIE coordinates; D- A( V5 l7 ?- n
653825 sigxp_tier was not reset when installing a new product suite4 s+ k" J6 S; w5 H h; H
657180 Enhancement: Tooltip for DRC markers
: ?4 i6 Y8 t: U/ o657187 SI model delete enhancement
4 {! p1 }4 O; }9 C657189 SI Model assign enhancement #20 t6 @/ c& Z+ n" }3 e$ r+ s
657501 Negative planes doesn't match with Film View) Z( G" {6 G% m+ ]9 m6 E. }
659543 Need a Report to show which Die Pins have no bond wire attached) T0 M0 O7 q* x- g4 ~4 @$ `9 A6 z3 Z
659661 Function needs for setting the rotation angle in finger by group.8 ^0 F2 \1 J* T: g
661477 Color192 window sections to be resizable
% \& l7 V6 D4 y3 A662215 Please add the function of renaming net by batch command.3 g. v1 W& X$ ?2 y" S: E
662325 Skill code example axlDBGetProperties.txt not correct# P* w& s+ M7 R+ G4 X p
662982 When you edit shape, ministat should always enable shape
1 C3 n" E$ ^% F9 C663260 Enhancement: ALG0051 message should be more specific
H( K/ {* o6 I i663754 Enhancement to create Device file when saving dra file on opening another design3 z1 S2 b6 J2 t3 |: \& |
664240 Add CNVPATH in User Preferences to place default CNV files5 Q) y5 U: P% ~( s% A9 F( H
665798 163BETA - provide graphical examples to show result of Flexible Shape Editor actions
! J( S f* U0 A( d666186 Enhancement FishEye functionality in Variant View Mode: S# u0 a5 O }3 R' t
666768 Temporary graphics for modules / groups do not reflect true size& S) k* w1 Y$ B) G0 E
666775 Update microvia to microvia DRC markings to avoid upper and lower case confusion
/ p4 X4 |: f# u6 b/ E2 x( I& p667773 Request for ability to set grid definition by entering simple formula. s- i+ I1 o/ t0 u$ v
668110 Customer wants to enter the value of radius when editing routes.# j& g0 }' v! r; r: I8 y( F
669373 Xnets are not formed correctly in CM. Up to 14 'extra' in a copy of the same design.
+ y+ d1 `" Q" H" A p669380 Add options for ts2dml in MI+ n$ ? `" a( Q0 k
669798 Add all 5 Dyn_Thermal_Con_Type property options to Via_Array.. Q1 v. U; G: `( Y
670775 Request to make the SKILL _axlSetDynamicsRotation and Mirror functions public
. x7 g7 {6 c0 f8 A+ Z2 X671194 Allegro not to crash when opening unsupported files
; O# b$ ?- B2 O: U* t9 `671337 Request performance improvement to access DML libraries from SigXplorer or PCB SI.$ f# c- o' o5 C+ B
671757 Handling of double quotes in HSPICE subckt.
) S$ t& P6 \$ [672930 ERROR [DRC0039] Tap may not be connected with the bus Check Entire net
$ {6 d1 ]! W! L9 m5 \674666 Report the wirebonds XY coordinates
y( F5 L* @* ?, B675118 Cline change width command enhancement% A$ W, {5 ]2 M+ J, g! h" w2 P
675151 Insert comment option for database elements
* H7 V( u6 O8 r/ C \+ R675398 RF PCB setup should automatically point at the project file if Allegro is launched form a project manager$ S* w( H2 G& r0 t; _6 j& ~* e) ]
675551 schematic to sip layout fail
% Q- m7 A) i6 b8 T. u- l676814 Signal Library command with Allegro performance license.
0 |- _4 S/ W: c+ m9 X676906 Add switch -regenerate_xnets to the dbdoctor dUI
" J2 c, P- x" F, B9 A; \677983 about setting of ibis2signoise option "-d" as default9 T, t1 h, a1 I N) Q9 d8 W; d4 X; l% o
678036 Request for a Physical design compare.
3 Z& T, o1 g& U3 t5 L678798 Identify DC nets command doesn't remove the RATSNEST_SCHEDULE7 V" \7 c3 f! \' p+ G" ?
679926 Testprep fails with no route keepin. Message in testprep.log ambigious at best1 y( D) u4 _. k4 V2 R
680586 Explanation of functions and macros in online help
7 r& j* L, m" P3 y4 n682695 Offset is outside or on pad edge. DEFAULT INTERNAL: REGULAR-PAD message needs rephrased
9 C6 O/ N) @" B% `3 j. r682865 When using PTC format IDF files don't use forward slashes.
# D' Y8 m. D% g2 S3 D684713 pin_count view needed for packages5 y* O# n6 c( h8 e% f7 ~2 ^% E8 W
684796 do not delete all vias with DRC for via array
& ?( h5 K7 T0 p& Z( O686103 Replace vias evenly spaced apart$ s( k. k) e2 F6 B7 g
686112 Add Connect and Slide keeps cline length$ l/ e$ A) o0 U" X8 l, X/ }
686122 Select objects by polygon9 {& O. y1 S6 \
687155 License for batch signoise command* O8 b K! F' k; x5 `
687187 BGA Full stagger matrix wizard generation
- t- h. C3 P5 U E1 _687201 Improvement in Find feature
/ U {( B& j0 }; s* F* n( V8 ~, ^* z7 F687685 Documentation of new properties in Variables block
2 e8 B u- u1 p$ _1 H. Q: W4 _688047 Include blank space in pin name as the illegal character in PDV user guide, `* U* _# @; y) } i
688830 renaming feature discrete library translator6 S5 E* w8 @: ~ M
689720 Need the ability to re-center Vis's in center of Pins when a Die is changed.
# O% y- a8 _7 j( K9 G2 _- v" U1 i695957 master.tag generated from the table design needs to contain the verilog representation of the sch.# s' W% P1 l8 f4 h3 P W& E
696661 Add ability in Offset Via Generator to add vias per a given Net
& t/ o4 S* T/ w0 Y. f1 k696812 provide description for axlCnsPurgeAll() skill function in doc& }: H& j1 m% G8 q' |. ?
697824 Components not installed of variant design should not be extracted into SigXplorer., p, E- P. _0 n0 X# a8 j
698097 Color Dialog form (color192) does not resize correctly* K: K: I; T/ s V
700262 Unable to add Signal Library Model paths in the Allegro Physical Viewer (part of the Allegro PCB SI -L tool)
& k( M+ T% `9 r8 C9 F* S700712 Defined pin locations are not used when using Die Text-in Wizard with default option Center pins on symbol origin
7 G' w( f# M6 a5 g0 l! W701514 axlCNSGetSpacing online documentation enhancement request regarding "bbvia_gap"6 K3 J9 c7 U- I. l
702190 Request support of Windows 2008 Server Editions.
. d* ?$ W: X5 w! i+ g6 y702613 Request SaveRefdesModelAssignments support the include original model path option.
! s) h$ ~( j# s/ i, P6 _703905 Need Hot Fix number Info on Help >> About
# s- v9 a0 z6 p$ ]) D5 P+ U9 S704594 Update symbol removes the text present on Package_Geometry/Silkscreen3 n0 l9 ^, x% I9 v
704899 Split Bundle Methodology Should Include a Next Function+ J7 F4 b$ h# `6 f$ P/ e
705601 Please make listnindex a public Skill command8 V7 I! A5 B. \3 R
705615 During Updating Symbol the text location and size are changed so Reset Text location is confusing; e0 G/ h8 I& P8 J& o
706165 idf import fails to expand drawing enough to accept text.
U5 c) f: U+ B' z2 O+ Q- M! y706457 Change type of the fourth optional argument for Mirror in axlGeoRotatePt to boolean
8 C- A. E5 m5 U0 S G8 e3 X( v/ Y706463 Add optional Character in the starting of each line of the file created by axlLogHeader
+ |& Z' w, k- O7 J9 s7 M& o706787 Fillet should remain when user slide the segment far from pin/via.
9 C2 T1 q! c- K- U3 \) _709119 Requesting a pull down menu with "Comp" and "Net" to be added in the Offset Via Generator: \* @" v s8 u. I0 G2 A# D
711837 remove the comma from the image of grid value separator' o; t. ~4 j C' W9 X
714840 Enhancement: Anti-etch can be recognized as Void element./ Y/ M% n% { ~/ G2 @, h* E
715454 Option to configure Design Entry HDL for Cadence Help4 S% U9 Q' K* O" o7 g/ L
715713 Enhancement for Wire Short Check during move feature
; ?- Q1 B0 h, c716671 About the log file of the na2 interface.$ f6 Z& [4 y' Y8 N
717722 Pad designer File > save as should have recent file name in file field
u" k: ~0 v5 u6 W718431 Enhancement request to have DRC checks on negative layers.4 \' y: ?" z+ \' }* Q$ f6 b2 _
719050 Log file should contain username date and time while creating or saving .DRA file: m! ^6 a p4 J5 `3 F g4 l
719514 Request length column be added to the Dangling Line Report
- F& |1 `+ _! ?: k$ A2 M720297 about "rip up thermal-relief clines"; @ {" b& W- j
722346 DRC checks for mismatches in labeling Net
4 a+ _3 ]' @/ \. p& b( W3 ~5 e3 c723661 Add *.pad in the File of type drop down menu when executing QVUpdate- x6 H- e. D0 p& E7 a" T/ M' Y" D
724832 Tackpoint move on a non standard wire bond -> *Error* difference: can't handle (2043.0 - nil); o( R- C" j, y2 y2 k/ ~5 I- C
726057 Request incremental DRC update when enabling DFA constraints.
( K% q, t$ q- d8 x# p( h4 ]/ Q728908 Add Color View Save and Load in Symbol Editor
6 I4 i* [/ C8 W729947 User would like a metal usage report
Q) {# y# D( m) i" R; t
4 g5 n0 @0 `& t
, t5 `% o% g+ F! M5 p0 {. ~7 iBUG CCRs3 N, H: [: n) S4 {
--------3 ?9 R& K# n0 Z U5 N5 P3 ^& X
2 g, r' I! g; [. E% Y; F' i/ q& `' a
( g6 c* h* X# a' iCCR Description1 Z( H3 r- n' b
----- ----------- - G+ d0 U1 l6 [ B# |
----- -----------) O6 Q' g5 |1 h9 O+ P7 Q8 D
, H I+ c* L7 L; U/ ^10116 Add Intersheet references does not work in Complex Hierarchy" @1 \6 }+ S5 r
11833 Junction not automatically placed when it should be.
i" W/ B1 t% b* p16310 Simple hierarchy, intersheet refs not refering to H-block D! d" c# v5 h0 l
19343 Request for intersheet reference to show grid reference zone
& k7 U9 c7 _6 T22424 Intersheet refs wont work on imported off-page connectors& t x1 t- M, X3 N" g
34275 Ibis2signoise fails with legal characters in file7 K2 N0 o$ g ~' j) p7 P1 S
85735 Cref annotations of the P_ID+00 Bus were missing9 Q) Q' m7 z: r8 o: G: \8 ^
134692 DDB_WARN: POWER_GROUP prop. not allowed wrongly coming8 C0 ^8 N2 l$ ]$ C& b+ k
199343 Stackup-Aware SigXplorer: o1 H6 S: x: h, W8 `0 Z0 f
207620 Part in MISC2.OLB has incorrect pin out
7 U _' [: i3 l: d, [270347 Changes to AXL SKILL must be Documented.7 a0 u7 N8 { k% g, t
283839 lm117 dropout voltage is too large
! d7 |; y) z4 K- O c7 p296826 Variant view displays library property* W, d+ t6 p2 W% a5 R3 ~5 P
299384 Part rotation resets the text to default position2 W* ~. T }( U) N( n# s) Z6 Y) W, F
328647 Replace Cache takes time for network libraries' v( K; [6 N, D. `( X p
340323 Dynamic shapes need same tweaks in 15.7 as in 15.5.1 to fill; g2 t! |% C! y" e A3 |$ |8 M% Y
341035 Dynamic shape fails to fill in design that has cline arcs
1 S+ F3 T* p7 ~4 U390692 Via not getting transferred through the Area Constraint from Allegro to Specctra
/ b3 y: h3 R5 W8 r; z405611 Environment variable for SIGNAL_INSTALL_DIR is resolved.' O9 O5 K3 O( |
428261 spaces at end of pin name Could not create new pin inst library correction utility, @: y0 B1 Q3 }1 @5 K9 n5 M; W7 ] G
436908 The color dialog window will loose the vertical scroll bar after being minimized.
5 u1 D# ?8 l6 h3 s& `2 V437369 Menu selection of Export > Libraries fails to issue the dlib command.4 { X6 P' A( | n; [
462783 Busname is too long/ S; c2 M: T& V5 l- L% b
495671 Unable to add the signal stubs due to the overlap between SIG_NAME & VALUE Props.
# n0 e% z: U1 ^) T509393 NC drill legend copies null nc_param.txt to current dir.( Y, L. M$ {. f6 N, y
512809 Window Prt.part.ptf shrinks by 30% and I have to maximize it.5 k C0 F6 M" |( N3 F ]
520802 Global Navigate Zoom to Object needs to remember last setting% s+ F9 a; V# n) D; k
528686 During text edit the cursor overlaps a letter rather than in between8 Y9 f* }& q- b8 Y( T7 D
531555 The diode BAV99 from library works inverted in compare with the graphical representation.
# _7 I+ j# ^/ O; N! ^6 T; d532603 Specifying TC1 and TC2 properties does not seem to have effect
$ }# a7 M+ m' {* X: N$ X) d- D547339 CM-SigXplorer extraction shows different topology in DE HDL vs PCB Editor% ?5 o6 t* k3 u$ t, c, F- {& K
548143 Dynamic shape on Etch TOP will not void properly.
# V& w7 P- N; ?. Z6 t550657 Importing registries do not setup printers from MWcontrol
+ r- {* q) C. Z5 o7 L8 }: i* n# I+ t552227 about die export padstack layer mapping
! ?* {- w! X& _553035 Cref Synonym and Netsbypage reports do not match netlist$ m# P$ E1 y. Y2 B Z) ~- i
558164 All variants are affected by function regardless of being called for; c3 Y1 x! h9 X
558692 Memory leak problem in loading marker files
; H+ W% j& i0 d5 y, Q2 k( x- q6 x565681 Filling in values in CM by using ctrl+c,ctrl+v and arrow keys is not working as it should.
# D B, n$ r6 Q0 o4 i# M/ P567606 PDV selecting pins in symbol editor shows pins off grid during move2 w6 B- J& n% f) O) J6 @
568049 Genview crashes( G S1 P: |3 z/ R9 |6 C( z
575353 Large box displayed with place manual-h and no RefDes variable set" ?! }* h" Z$ l
581848 not able to edit Padstack Boundary
4 o5 i$ i9 \8 h$ K4 i591847 Add Intersheet References does not work on simple H design.
" z( u, J7 b: B6 }) ?3 S/ @* n$ A6 J592381 Physical Min/Max line width values not check on internal rows or forms.
2 o @+ W' ^# n593076 Cannot redisplay an invisible OFFPAGE connector's name
( R9 ^- u( m5 O) }/ x, H' F8 d598038 Detail button of Markers window with 16.01
. F7 U/ N0 C9 W M" x6 B$ e) ^601415 Allegro Design Entry Tutorial corrections.0 F; o7 H' R: L1 ~
601531 When using the place manual command and rotating part a ghost image is left behind
4 S% ~8 I# X$ j603181 Formula to calculate the Actual Temperature for Smoke is incorrect.
8 }# K" e! A5 |: E V604965 need to document how tcl cmd addComponent handles property values with spaces0 d3 A" K4 L* A
605843 Aliased nets do not fully dehighlight when next net is highlighted/ |. G3 c7 o d) N
606493 Targeted nets are not remaining targets
: r+ n; k% K% _9 t: Z) p h608150 TestPrep generation is creating DRC errors* b5 [$ S7 f& K+ ~' F2 }+ i; d
608787 Missing Constraints Report: `: ~6 W6 E6 G$ f
608942 PDF Publisher output misaligns text in tables6 a$ e6 n) A6 R- T% X- D4 d& A
612511 Error in Flow Tutorial regarding checking default user units- U, K4 A' }" t% }3 n
612982 VLIM model giving error that line is too long6 {6 o2 a( k- { {
613194 Adding wire bonds with current selection does not yield DRC's, mismatching Allow DRC violations option.& Q" w$ G [ v
613738 Variant BOM report lists identical parts in separate lines due to POWER_GROUP- |9 C# U1 V$ F
617146 Symbol fails to place through Component Browser
6 T7 c2 ^) i+ ~ P617327 Change root operation results in SCM crash
9 ^1 O g- R" T- y) g618150 Property Editor Functionality
f+ G$ ^0 _0 X4 D! r" s4 a618617 Enabling strokes requires checking/unchecking options boxes; Y! R/ \$ I5 L3 \
618771 PDV error SPLBPD-382 when importing from APD.
3 r# ?7 Z# a$ b8 L6 H619053 Diff Pair problem with creating them in DEHDL.
8 ]3 u0 {! z9 n619849 Hierarchical Blocks Loosing reference6 ^2 r( {9 h: V8 D
620001 Measurement's Maximum range calculation is not correct
9 U4 M" h/ T) I620343 Bogus error during schematic write
( P7 |& c- C- L620826 Changing the units of dimensions does not work
: _; ]1 q% e# b. c- u621163 Ambiguity about the how is the ?start of the wire" defined in CDNSIP for ADRC Wire to bondfinger optical short
7 l7 O0 z' ~- q" \6 |, |622263 Drill Customization sort order for oval oblong slots should account for Size Y
1 H7 p3 g# ~+ d' L% r/ Z622583 Allegro produces erroneous error msg - symbol not found when the placebound is too large for the board.
8 x2 t3 n3 p2 _& s5 h622692 Why is VGSR negative for N-channel MOSFETs
) N% J7 X D0 S9 H0 U/ e624378 Device file content conflict M8 d8 m; U2 a# ?
624492 Model Editor finds the wrong model definition for BAV99* ~! i! O$ Y8 q- R9 x
625462 Symbol pins Property are lost when once stretched+ [8 y; L) i; V( R3 K5 t: r/ ?% H, \
625519 hspice_mt is not used in Channel Analysis simulation" l. p1 \. W4 J5 t# e4 t' Y" s
626674 Allegro CDS_SITE setting don't appear to match documentation( f' J9 ], u1 @: Y9 j
627018 Find Net in instance mode displays twice
/ [' l, ^ g$ i* b627864 EDIF c2esch crashes
5 `) K# W9 m' W' e$ f: j628077 Degas not voiding correctly
& U0 k' [* ]: N* L, v628265 no "Unused Blind/Buried Via"Report in APD products. H4 k: i+ [$ \5 B0 a# `
628845 Markers> Packager menu is unselectable even after pxl.mkr is created.
! n* S) j: x' {/ c7 C1 t631344 Mouse Wheel Scroll misses the "along with the Control Button"
' I8 Q! E+ ^" c& R# C633130 The Verilog netlis is wrong% b9 `' a @% s+ S) n
633223 Running skill from a HDL script causes segmentation fault.* }0 j! H& o" F$ u
633473 INPUT_SCRIPT inconsistency when removed from .cpm file2 y/ r" ^& \) {6 V6 i/ U
634075 draw_etch_outline doesn't work for circular shape/arcs$ E* u' Z3 P2 `" l
635779 Allegro OpenGL distorting text at certain zoom levels
3 c7 \+ h" k( A636215 Allegro documentation for Export Parameters is incorrect7 B% x7 B6 v( d7 Q+ K( G
636688 Signal Model Assignment UI and Find filter association is broken
" a2 {& \# @) ~636819 Documentation wrongly indicates that DFA Analysis in unavailable in XL( y% S r* F: J: w# m8 W" a
637379 No column for ROOM shown in Constraint Manager
& E. A/ o+ h% R2 z* F- G638140 Intersheet References not offsetting relative to Port' u; ? C' O7 V7 L" ]& C
638670 Testprep parameters - padstack selections - Bottom Side replacement text not entirely visible.8 y0 _6 C$ z% ]5 S+ V
638987 Change command hangs on customer?s database
% f! p- {% T! [( i" p639052 Database Objects Preventing Layer From Being Deleted report fails to run
k f9 {+ @ e- D1 k7 s639698 HOME variable defined with %USERNAME% doesn't use value of variable.
0 l; M9 U( w1 r639829 After setting Zoom key(F10) to a new alias Tool Tip is missing the key number, w' g8 N$ O8 T2 V, J
640127 Correct IDF documentation regarding UNOWNED objects9 O5 o% c; I$ w) }3 E. k& f/ X! l9 [
640293 performance issues with scm and large pin count devices* j& r. ~- F% r! j' K& T7 A$ S
640314 The number of menus written in DE-HDL UserGuide is untrue for Unix/Linux users.1 W4 B$ x- \; O& }& r8 s
641503 Stop running the VAN check on a PLUMBING body symbol in PDV s1 B, c* N( N9 [' W; L9 C
641676 Incorrect link to assign refdes help
4 L% d: C$ n, m. E! B' I642053 Drag Connected Objects icon is always display as on0 _: Q, a. o$ {
642299 Switch the windows mode by set command4 u" K8 @! ?/ Q
642436 Save As symbol in part editor is not working fine
: L8 q9 B3 j! _9 J# s3 k0 _642713 Materials are not refreshed when material name have only numbers.1 f; X3 {% |! A7 h2 x
642873 Dynamic shapes out of date message refers to Setup Drawing Options4 l, w+ V* V* s6 [
643721 Attributes with Null values in symbol.css files are removed when saved in PDV
+ {6 N2 J$ z2 c643949 Can not create Region-Class-Class for same net class.
/ ^( P2 f# U v644016 APD crashes when creating a tile from LEF file1 T# E% }: Y T. y* |
644733 Import reference text file gives incorrect results# O9 @6 j/ F s& q5 D
644879 Change forms to enforce naming of lib.defs file
# J5 [( x3 ]3 A% D* F- d3 R645046 SG1525A PWM model is reporting unmodel pins and producing incorrect results
9 d+ l0 t- o, F# Y9 }- b645427 The save button is not enabled on changing the line width
/ p' T& d: Y1 @# f4 ?645996 con2con fails to parse ppt file correctly
, h7 \ q. P, y$ Q646175 Please modify the limit length of "Allegro PCB Editor Limits" correctly.7 _ v% X& N! g2 s% w
647555 Drill Customization text Non-standard Drill is not readable.# Q9 v Y6 f. ]8 N/ n% ^/ v$ e- W/ j4 o
647628 Annotate Type should be removed from PPT Option set files and documentation
$ F2 O0 ^8 @. U648443 Launching SCM without a license is not reported in debug.log
) G; ^5 r7 u1 r. B6 ]4 B* {8 n649222 Silent install adds extra License Server to CDS_LIC_FILE on the client
' b8 k3 P6 |7 P; h: F650558 Die Pad layer changed after refresh padstack- r r, k) p! L% \" O
650997 Incorrect Pin Shape in CIS Explorer Footprint window/ d1 M; I. G5 o& Y J, J/ s
651000 "Wire length over parent die" violation is incorrect.
6 O: ?7 ~# s! s- ~' O5 y# o651153 Results for imported CSV inconsistent in PDV
& e2 \& |5 \* O5 |1 J+ T651521 Resizing the display color visibility dialog box corrupts the display6 W u6 B. H1 x0 s$ l1 x- @: F
651526 Parts are missing in a advance analysis library list document and font size issue
6 Y5 J' ~+ }$ d% }' ~4 l) O1 ~3 [651532 Scroll bars disappear after minimizing the color visibility form
# N# b# c: _6 U+ [8 m: D4 O- x652050 Append waveform does not work in 16.2 for .dat files created in previous release with import text format+ P4 A1 E3 d9 L
652904 significantly low performance issues when using edit interface to delete ports of block
% a: W" n& |3 f# x) Q' Q0 N5 J653067 Incorrect warning SPMHNI-198 - Pin name is not legal and will be replaced by `$#?
# Z# a5 B* q& e* }& w" N653784 Off-page connector name change to internal starting like "I12345555"/ Q& F: I/ V4 p4 F( t: e
654580 Save As should update lib.defs without executing the edit die operation
8 [ L% y y6 ^/ U656282 BGA Generator adds outline and RefDes to wrong subclass- e. x4 J8 W/ [
656723 visibility of clines in 3d viewer needs ALL instead of just CON field in layers. J# h/ [& b+ s, L, d
657836 Text crop on User Preferences Editor form
- L! p6 ?8 c3 v& l0 B5 t658347 Rule Continuous Soldermask Coverage Check should not work on Cline Segments
% b5 Q! D, u5 F2 r- C. }659437 Move group fails to display anything with Open GL enabled.
- [. d5 `- K+ ^660937 Import techfile fails with etch on layer yet layer has no etch
/ K, Q7 o8 T: y$ E; N2 J( F661369 Importing design fails with the SPCOCN-1158 error when DBL_STR_LEN 'ON'1 Q) e* O& i/ E0 k' ]: X8 f
661754 Hyperlink publish pdf to correct page but wrong grid location
8 `1 b- t7 @( G5 ?+ X% W D662622 Export Physical reports error Output Layout Filename contains space
6 q# O) q% y5 |5 i) U/ {* J2 k662918 Skill code example for axlReportRegister does not work
?! n3 V5 w0 F662971 Moving Bondwires disconnect bondfingers. W/ _9 r- F8 c# U% g- U5 F
663088 Cannot add connect to a C-line in Etch Edit Mode# U& _: ~2 z. A' a8 O
663220 IMPORT_HFS_HARDSEC_ON_SWAP_PINS directive causes error on save in DEHDL j$ ?1 D4 L/ a, E
663726 ?Each? menu under RefDes is missing in BOM HDL user guide
/ k u/ K: H: }) `9 _664764 Material changes when layer type is changed# t6 \( L' ^. T! G5 h
664900 Project manager User Preferences Editor form has text crop.
+ G. q) s/ g x665236 Unable to import a Quartus-II version 9.0 pin file.
; }7 h% w& p% e665389 Spread between voids not working for customer design
5 L. a! b7 C) |* c% x665413 In File> "Import and Export"> "Import-ECO pin table" the NEXT button does nothing.3 {" t$ _ @% c) i3 b! A' c
665451 Import - Part logic - information popup window has incorrect user preferences Editor Category6 q3 _7 F- m8 d! x( }
665661 Wirebond Die Escape Generator failed to generate Clines
; L9 V+ b, G" Q! b, D666099 Mandating at least one symbol with sizable pins for using size..1(not for size-1..0) SPLBPD-310/SPLBPD-309 on reload7 U6 ~, N4 _! `8 t( E5 [
666667 Relational Table View Browsing Issue6 G0 H" z% }" K& x+ x7 u; N9 S
667286 import IFF No Component Shape Line Via found in IFF file.* q; O& c( c6 i6 _, {% ^
667751 db(v(out)) and vdb(out) gives different results for FFT f0 ?) M+ u4 @2 m# C
668080 Improve handling of curved routes/ a4 q. A/ C e1 ]% W F v
668393 Dielectric constant or loss tangent values do not update when changing conductor
7 x, [3 A' }: B* Y668876 Text on the Add button is crop on the Edit via list form.8 p1 H/ W' B1 q F% X7 J$ V! U
668892 Incorrect Parallel Length data in parallelism report
% s" A2 A: D& [! Q) E# s% s669206 Parallelism rule causing significant performance issues during DRC update
7 r; ?$ e Q9 F. ?3 `! o" J669238 Unable to use permanent highlighting for groups in version 16.x
$ U* B. K8 x" V8 x+ v669323 Allegro PCB SI User Guide Doc page 229 ignoring vias needs to be updated4 I/ P/ P; w$ X' Y: v* _' j
669336 Error in documentation of DE HDL Reference Guide) G, x7 w& p! X/ f; q
670874 getVersion() function not reporting tool version
) q1 x# O* s, _) j n: u) i671811 Allegro extracta fails with more than 10 output files
) i d$ [$ Y: p4 R3 ?" _672420 User defined property added to component instance is a function property in Allegro
2 M u8 J) P7 W5 W+ W* p, k, q# D672614 translator converts the symbol "\" in the original Spice model to "[url=]\\\\[/url]"+ Q3 l2 a- w2 Y
672615 Translator generates 6 external nodes should only have up to 5 nodes; L- ?, y8 W% [ h8 Y) M; l
672618 Translator generates statement in the dml file: Language=hspice causing Spectre run errors, N9 @/ m: l- p; ]5 P
672715 Steam_out takes a long time and then fails but the .log file reports a successful export
& e: X2 B0 }6 T! w673279 Same characters are listed as both valid and invalid in naming rules.
+ Z8 H* m" l3 ~& T% _) [673410 search by net name is finding electrical4 y/ V+ k3 B; F1 c$ F; [/ t; g. J& p
674058 Incorrect Variant Report& O0 ~5 R: `5 U. _# ?) l/ {2 t6 x
674291 Library Explorer fails to start and I receive a 'Runtime Error!' pop-up! D' `- T9 y8 P5 e+ [
674555 If the DSN filename contains spaces, autobackup will not write any DBK files to
8 ^! z$ e; ]$ f675192 Adding a second BGA caused dsa_api.c to crash
2 k. s& G. a1 `675231 SiP Layout doesn't handle ! characters in port names from Verilog and OpenAccess., l1 s; H/ P% d5 q2 m
675562 axlWindowFit() documentation needs to be changed.! N1 Y# V2 ]( x( A0 F; K3 B
675783 SiP Wirebond moving a BF sometimes results in the BF placement on the guideline to become unplaced from alignment option
7 c2 x# ~- i; I) W3 p% C3 r: {676201 Cross section impedance not calculating with single license9 D3 c, Q8 b) m5 T8 A @
676601 behavior of launch product from library manager
% b1 |5 m2 q+ C- w677582 mirror of die component on sip designs: c% @- z! c0 }) t ~+ j
678013 Error: Symbol not found, though symbol is mapped in psmpath
- }. J: y9 [+ O8 @0 Z% @. x678427 repeatedly placed symbols has strange instance name& c3 B. F& [! M6 h8 t" A( L0 ?; ^
678538 Why derive database does not transfer the Schematic Part property to CIS. w0 c8 Q8 D6 O7 O, Z% V
678814 Spin a temp group will not rotate the symbol4 g4 B1 A2 V: ~- H3 N4 _
678851 Difference in lengths in 16.01 and 16.24 l% \2 a6 E* Z9 _4 G
678884 dbdoctor fixes corruption and then it's reintroduced# V. W% r; n; Y; L) D+ G2 ?1 `
679224 dbdoctor states it fixes an error but the error returns' r' I: H8 a; W- S/ g' `
681197 Report generator Hangs Up Allegro PCB Editor! ^. d7 C3 ]- V7 }6 w- o8 |
682135 Justification of $PN placeholders not working in 16.2 release, {" C, r* V) }
682204 Cdsserv.exe and cdsqmgr.exe crashes using 16.2 release on Windows
% l# p; d7 ]' l1 S( s7 N, y6 |682331 Incorrect reference to the middle mouse button.( O9 M$ Z s' u' m+ }* K+ i
683146 export variant path appears wrong in output folder while two DSN are open simultaneously
7 Z% Z. T' z' B! B& i9 Z% `0 U Y683182 DRC0037 shows incorrect Alternate Net Alias.1 T- o, T/ A' o+ l
683379 ERROR in Measurement ConversionGain_XRange$ B; \1 `. X$ }' ~) t1 {: M3 i
684180 Sizable pins and vector pins cannot reside together in a component.
. j! ]3 b' V: W6 ~9 E {684661 via array created wrong results/ l8 |8 R7 ?# e5 I+ ]5 W0 R
684700 via array can not be placed on both sides of the cline
. Y0 n* f$ R; s( z1 n684912 16.2 documentation is incorrect for axlDeleteFillet
4 v$ ^) B8 Z% |: u+ s1 ?" V684915 Incorrect mention of creating graphics template in the PDV user guide' ]: Y- j3 s6 k) k/ [. \% t
685685 When the customer tried to merge shapes, they disappeared and do not merge.! p, Z2 d, F. f# M
686338 ERROR #8012 Database Operation Failed with MS SQL database
' }* J* I& @3 g. [6 |' \1 C- z686560 Changing pin group property after pin swap resets pin numbers' i6 k0 g9 \- r W) k6 k, u3 [1 `
686736 Load property does not propagate to the associated MECH part
. K; c: W9 A+ N687008 ERROR 8020 after removing Place Icon
) u8 u5 [6 ~4 Z8 V. D P687074 Part disappears when you open it
+ W$ L# S, @& K: [! I: l8 Z/ r, {687354 Not able to create allegro netlist 228 ERROR(SPCODD-228): Cannot package8 Q3 N3 o# T \( A5 O
687385 Publish PDF outputs the net name (with underscore) overlaps with wire.4 c+ L! d4 y) m
687708 Smoke deration calculations for Capacitor- B+ r! Q7 D' a9 r; i
687715 Getting Warning TJL will not be smoke checked: u7 L& o, O4 C1 g( L6 j
688606 Inconsistency in synchronization between bias display and icon
/ N9 A7 i+ g0 d( |) u. U, ^/ T689542 Comma in ESpice model name causes simulation failure& ]7 W1 [1 l; m3 a, o0 V
690112 Ignored nets are displayed in simulated crosstalk worksheet in CM& B9 f, S# u4 k
691668 Stimulus editor hangs on doing change type8 U5 @# h7 z6 O" [: ^$ p. U2 N
691740 crash when setting coincident uvias in CM beta testing 16.35 K% R% Z8 X8 I% c
694139 Case difference of net and bus while generating FPGA netlist
2 ~& \9 s$ {# }% F. u* m$ z$ z( _6 E694716 Waveforms are flat when using IO b-element in HSpice: k& ]8 c: x% D
695109 Incorrect Diff-pair topology extracted by Paksi-E field solver U9 V8 @ i7 Q3 i3 W
695431 csv2ptf fails without providing any error message
! o/ b7 v4 N( i) o696273 Shape disappears when updated in CDNSIP 16.01 and not following the constraints
: P0 P0 L- U3 \8 U0 ?696534 Pin Visibility check box doesn't work while creating part from spreadsheet editor
- m0 R1 R; a' h698494 Shape not getting filled correctly
, Q, |4 B& A0 k- s700160 Error: TVCurve must start at time zero ./ x7 E2 D, w U% @
700644 Allegro Crashes on doing Zoom In
) L8 e1 h9 U% o+ L' u& i8 F- a1 L700725 Create Fanout with Via structure add structure from Top to Int. for bottom pins
0 z, i1 r& Q7 S0 W; _ J) W6 i701128 Inconsistent warning message : TBreak (Tknee)is less than Simulation Temperature
: ^, c \; m/ A0 L702557 Incorrect Behavior with FSP 2 FPGA Option License: `# K2 `4 m( ^; A
703324 Cross probing board DRC objects to CM DRC spreadsheet fails to zoom in3 ?9 s- C' R" o, s! k
704268 remove ARC and TOGGLE rmb options when in add rectangle or add circle command
/ f A" K: O: C0 N$ o ^- ^) ~704475 Allegro SI change editor to Allegro PCB XL causes menu problems
: z# S* D d3 N! |. @, @6 C705902 ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
" O- {& @$ G) J7 \705903 Cannot remove a matrix view after modifying the connections
7 Q3 v) T1 d) y, O706169 IDF in error has spelling mistake1 I: Q3 J- Z* T# L6 f& S/ w
706613 Diff pair is not extracting properly through design link.
% |1 g8 M5 E7 `- N/ T4 G: d) x706729 Import properties fails with ERROR [IMP0020]/ g, c8 B) X4 q( C+ s8 h; f: \
708134 Place > Manually command menus not refreshing the Placement list% E5 |5 D5 r; L: r9 H, c6 j: f
708145 Creating a netlist with Rev. 57AQ is not formatting correctly# k) m' `' h- N7 b; \% I
708634 Shapes getting incorrectly displayed in 16.2
* g* k" h) ~3 { F/ X7 Z6 {- W g710279 ERROR 8020# Place component operation failed.
" x2 r- I; I5 C. K710859 Unable to create Diff Pair from Autosetup& W! N; h- \3 w5 \1 q' ~
711739 selecting one component/symbol of class IC can move unrelated component due to incorrect group membership.# j, T6 n* m B3 h6 n+ {% V$ ^5 K
712299 Internal application error while creating new design- _# w5 P I( L7 U( @: \7 O4 _
712898 Netrev should not read PARENT_PPT_PART property value while importing the logic, due to which import logic fails |) N& |5 o) ~# Z% M7 E3 u+ |. x
713465 Problems with dynamic shape creation over routed full-arcs diffpairs2 k) D4 l. J9 [3 D3 f' x
713480 Display issue when adding a custom property to the first bit of the bus.
- {! ]. w* y) W A7 r( u5 M3 o714072 Error while linking database part) `1 Y5 m; E! t4 L5 E: v
716097 Specctra is crash during route., _1 _4 s p2 Y; u8 m! X! i
716212 PACK_SHORT property gives package error for visible POWER pins
# L7 O$ c$ f6 E5 W, J6 q+ o/ J" O717484 Dynamic shape creating voids when moving a symbol4 [% V; `0 F9 c; l
718151 Geometry not selected when we click tab for selection filter in pad designer
% y% N6 O# T6 d! n- ^* e; g9 m! O720092 Difference of behavior for slide for segments in options tab & RMB options
6 F' W- T6 f0 A720191 Delay tune cannot keep the Gap if the diffpair segment is diagonal.
; H: X1 W2 S9 a721415 Two buses are connected without a warning when moved on top of each other
) T. O+ [4 }% O- D1 a721938 Cross-Section open error1 x" y1 ?9 h2 \2 v4 V1 ?/ N
722997 Hyperlink function does not work if zone info. includes hyphen
* P' z7 |0 |1 B* D; p, B9 j723146 Pb during compilation using predicate getFileStrings
) S" P! r1 [1 q5 U! c) Y723159 Typographical Error under "Synchronizing PTF Information" section
. E* E/ ?/ s5 ?2 R, ~723235 client install results in incorrect, redundant, and problematic cds_lic_file variable
0 H' f9 ]% j( ]. c3 S8 e7 r724414 State Wins Over Design does not reset the subdesign_suffix block values
. r( h$ X% y% U2 y724969 Allegro crashes when using place replicate function4 L3 J8 ^. N( b- \' Y; o
725852 Impedance has little difference - BEM2D
) D- s) |: A0 S- c/ y" v726731 SiP - Wirebond -> Edit -> select bond finger -> RMB Change characteristics results in bf not following snap1 D/ D9 g' j3 U
726763 crash during logic import in Allegro CM enabled flow
! _& F5 A5 X. T! i" }6 I727663 Remove Subclass in My Favorites (Color Dialog) doesn't refresh properly9 h7 W9 F1 Z8 ]- F0 H G9 C
729496 Build error in 16.3 and 16.4 cdnsip.exe |
|
/1 
发表于 2009-12-9 13:24
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
