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" Z% B' P( P' l4 {C:\Cadence\SPB_16.3\tools\capture\allegro.cfg
$ z2 D/ n) p2 }, ZSpawning... "C:\Cadence\SPB_16.3\tools\capture\pstswp.exe" -pst -d "e:\project\hi3512\hardware\hi3511dmeb_sch_ver_b.dsn" -n "E:\PROJECT\HI3512\HARDWARE\ALLEGRO" -c "C:\Cadence\SPB_16.3\tools\capture\allegro.cfg" -v 3 -w -l 31 -s "" -j "PCB Footprint"
7 w! ?* u' E1 O, @( u$ GScanning netlist files ...; w) O* `2 B" F9 F, b
Loading... E:\PROJECT\HI3512\HARDWARE\ALLEGRO/pstchip.dat' Q+ b& x/ g$ I: W
#248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'C_STC7343_47UF'. Each section must have at least one non-common pin.
$ f% C7 f4 ]* \7 u: t r" h Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.
) Z5 X# \! O) i% z8 ]5 R& } ERROR(SPCODD-47): Packaging can not complete because the file E:/PROJECT/HI3512/HARDWARE/ALLEGRO/pstchip.dat could not be loaded. There might be syntax errors in this file. Ensure that the syntax is correct before proceeding.#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the design before packaging.' p. W- Z, b5 ?9 t" i3 c9 M
#1 Error [ALG0036] Unable to read logical netlist data.& u5 {) D( T. m3 Z! N
Exiting... "C:\Cadence\SPB_16.3\tools\capture\pstswp.exe" -pst -d "e:\project\hi3512\hardware\hi3511dmeb_sch_ver_b.dsn" -n "E:\PROJECT\HI3512\HARDWARE\ALLEGRO" -c "C:\Cadence\SPB_16.3\tools\capture\allegro.cfg" -v 3 -w -l 31 -s "" -j "PCB Footprint"
) N9 h- _ v! L6 j5 ?" F( [ O5 g5 Q) \, h7 x/ ]) F. c: s3 ?
*** Done ***+ K2 | A. g4 g* z: J' t* m
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发表于 2011-4-8 14:55
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