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本帖最后由 紫菁 于 2017-9-14 14:13 编辑
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Cadence SPB OrCAD 16.5 最新的升级补丁，版本号16.50.47，修正内容如下：
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DATE: 09-6-2013 HOTFIX VERSION: 047
7 v+ M# k! u# \CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1095533 CONCEPT_HDL CORE changing visibility for $PNN results in crash in windows mode
\+ d% ^8 s9 @" c1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form% q) g0 N7 ?$ K$ L
1156102 PCB_LIBRARIAN CORE PDV severe performance degradation on Linux platform makes PDV counter productive after some time
# q- A p6 Q$ K$ q1161781 CONSTRAINT_MGR CONCEPT_HDL SigXp crash when selecting ECset in design
5 ~) t, @: I3 Y8 U" W& V1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin. k/ c8 I0 d8 O
1167887 F2B OTHER Improve message on symbol to schematic generation7 T9 _5 u- j$ N0 V. c6 A* F
1168496 ALLEGRO_EDITOR SCHEM_FTB Export Physical Crashes when netreving the board7 D8 D$ _8 Y( v# m3 w, Z4 ]' g
1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check' L( m& S( ~* N) {( b
1169593 CONCEPT_HDL PDF Published PDF file\'s hyperlinks do not work fine when user click 1D10 or 2A10.
; G3 L& J4 c, }1 B! ?1 ]& @1169984 F2B PACKAGERXL Error Mapping cset when packaging but not in CM Audit1 Q# p: T: [7 X& }! ?
1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window.
; k/ Z! n; v, [3 ~2 x# ?1172597 ALLEGRO_EDITOR DATABASE Board cannot be unlocked using Password used while locking
- ]- p0 d$ p; i- k" t+ q7 N1172938 ALLEGRO_EDITOR PLOTTING Export IPF probrem& L# `* E: s# \ K: W* }" o# u
1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via
/ U6 i( U3 X+ d. E V- R3 p/ e1173829 ALLEGRO_EDITOR MANUFACT Backdrill completes even though a stub exceeds the MAX_PTH_STUB value
5 ]& ]+ y, ~; O# _8 o, Y2 C' y. R1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section\'s parameters was not applied immediately after importing a DCF on the Constraint Manager.
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发表于 2013-9-11 09:53
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