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楼主,经过测试你这个是完全可以导出网表的。如下:1 Z5 O( @2 X- A- V% J8 {3 S
Netlisting the design 6 U; S7 W/ j' u( r
*
& T6 M3 j0 Q; t" b7 @: f! p********************************************************************************
- E$ r: ?! ~) c0 e0 X3 l3 {Design Name:9 ]9 F: d1 w5 r a* V: m
e:\my documents\123\etc_1+1.dsn
5 e( n# [" Y. S8 XNetlist Directory:
8 f8 ^6 }1 S! q4 j7 CE:\MY DOCUMENTS\123\112 w0 A3 c z' u8 A
Configuration File:
9 I! b( Q: k" x' u; h, J& o, uD:\Cadence\SPB_16.2\tools\capture\allegro.cfg
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/ w# k* Z- T3 cSpawning... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "e:\my documents\123\etc_1+1.dsn" -n "E:\MY DOCUMENTS\123\11" -c "D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"2 ~) i0 ~3 ] {" g2 T T# A) d- m
Scanning netlist files ...+ _" L7 [% }6 q& A* H- o
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Loading... E:\MY DOCUMENTS\123\11/pstchip.dat
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Loading... E:\MY DOCUMENTS\123\11/pstchip.dat
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5 H( H0 L& I$ L0 Q3 E, xLoading... E:\MY DOCUMENTS\123\11/pstxprt.dat( Z# Y3 ?, O- |3 n/ E9 _1 d+ r' h' k
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Loading... E:\MY DOCUMENTS\123\11/pstxnet.dat
9 Q9 H1 W; L" Y4 npackaging the design view...2 v; c Y9 w0 U; S( I4 k
! l& j3 x/ ?. m' J# M( DExiting... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "e:\my documents\123\etc_1+1.dsn" -n "E:\MY DOCUMENTS\123\11" -c "D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"% o3 `# d, |: q& L: t, V
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*** Done ***& `( c6 {1 R8 z$ P2 I- V; J s2 t9 F0 M
建议,你将你的设计文件*.dsn文件单独拷贝到别的文件夹,重新使用orcad打开,保存后再次生成网表试试。 |
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