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LBSALE[10]LBSALEMIXED-SIGNAL AND DSP DESIGN TECHNIQUES* O1 T4 i# Y l' U: q
SECTION 1
& [6 w, J1 @" q6 Z2 I- X$ {3 P: JINTRODUCTION% J) Y% e/ \' _( g
SECTION 2
% K* `; W- k2 JSAMPLED DATA SYSTEMS
/ t* k+ V( D" t0 N! J, s Discrete Time Sampling of Analog Signals) v, r, \8 z8 u$ q, u4 n
ADC and DAC Static Transfer Functions and DC Errors; ]8 r$ J. ]. @% ^
AC Errors in Data Converters( r8 J% l2 J4 N
DAC Dynamic Performance. p/ {. D+ `) W0 _* Y& U7 r
SECTION 3
L+ M& @& e2 M# `* Y( Y% b, m& c7 j% zADCs FOR DSP APPLICATIONS |$ Y" V, v- R9 s
Successive Approximation ADCs
- [7 [; l% b0 D3 L$ d: K" P8 U+ ? Sigma-Delta ADCs
4 F" I1 [- o/ g0 j Flash Converters# [# d) B$ u. E- o- h; r
Subranging (Pipelined) ADCs- ?9 `- T. J' X S3 Q
Bit-Per-Stage (Serial, or Ripple) ADCs
8 a2 Q# \4 s& ?/ uSECTION 4* u Q% u0 w& I
DACs FOR DSP APPLICATIONS/ r& c+ S% }9 E4 @) T! r0 [5 j/ h
DAC Structures
6 R4 S: x ]; ^; n Low Distortion DAC Architectures
" s2 u W3 S; u DAC Logic4 L. C) `3 Z+ l6 W
Sigma-Delta DACs2 c U& ?" }0 X: R: n; M
Direct Digital Synthesis (DDS)* D6 ?1 i- t' W
SECTION 5+ g# g( [" V* R0 `2 q; {, z% g6 s
FAST FOURIER TRANSFORMS
3 L, Q+ G) Q& Q2 P The Discrete Fourier Transform# n$ V) u1 u: _: }6 V: _
The Fast Fourier Transform5 w- {; e& I9 \- i( Z: J
FFT Hardware Implementation and Benchmarks/ X( D3 y0 W. ^$ M; V
DSP Requirements for Real Time FFT Applications
* H$ p* J# [$ H4 | n! W) n1 j Spectral Leakage and Windowing
, v5 C; z0 t( i USECTION 6) g: d) ]3 O+ q/ s# d4 ~
DIGITAL FILTERS
+ t6 {; }' l$ @1 H* e& N) r! R& d. \ Finite Impulse Response (FIR) Filters
1 I2 b' { S+ s! b+ o Infinite Impulse Response (IIR) Filters
* n" B0 _. A" b; V+ M- r( C2 ~5 x Multirate Filters
1 {' @( S! {2 I# f3 q6 X7 | Adaptive Filters" H& v l- X9 b$ T; j/ r
SECTION 7+ @4 @ J5 ~* n& l
DSP HARDWARE4 p2 y& w6 B! m! [% `
Microcontrollers, Microprocessors, and Digital Signal$ c3 ~, d+ s9 X3 a; O& Y) A
Processors (DSPs)
/ Z& {7 B% j( {) D$ @# _5 J DSP Requirements
0 h" m: }: W& M7 M* Q# z1 I. N E ADSP-21xx 16-Bit Fixed-Point DSP Core
0 m$ r/ v, N5 ?! S# f" [$ d Fixed-Point Versus Floating Point
% P8 N1 k+ d% s# {: d& h2 m ADI SHARC® Floating Point DSPs5 v5 g- l: I# }
ADSP-2116x Single-Instruction, Multiple Data (SIMD) ^( B3 T/ d& P% k# c8 b
Core Architecture7 Z6 V% n' k9 ]* r& f
TigerSHARC™: The ADSP-TS001 Static Superscalar/ F. i% F1 t, ~$ C5 t. o/ h) [( n
DSP4 B( \- h9 b9 a" Q# g- d
DSP Benchmarks3 p X! |7 ~3 ^* m/ e* R {
DSP Evaluation and Development Tools9 O- G; H( I) C+ @
SECTION 8
$ ^4 p; r0 H/ Y; s" z @: ?INTERFACING TO DSPs6 c6 g T0 J" b6 _1 c1 O
Parallel Interfacing to DSP Processors: Reading Data
! b& { k6 H* K. f( F* c! e$ zFrom Memory-Mapped Peripheral ADCs( E+ C9 u' x0 ~- o' D+ }) w$ c
Parallel Interfacing to DSP Processors: Writing Data to
; s8 k2 O, s' S8 C4 O! W1 CMemory-Mapped DACs1 B, t: }; o* E% Q" n% D0 J q
Serial Interfacing to DSP Processors4 ^/ u0 V6 t6 ^8 K
Interfacing I/O Ports, Analog Front Ends, and Codecs to
5 L1 m7 Q# F, R3 U7 L3 QDSPs
( y* _9 S/ V' l3 K: o$ i7 ~ DSP System Interface: B) L$ N$ H' r1 o2 h$ \
SECTION 9) O( U# h8 F# D, }
DSP APPLICATIONS
9 }$ [, o$ E8 H. a+ F: X- \9 I High Performance Modems for Plain Old Telephone
% P8 l, Z! Y0 a- h6 G/ S$ HService (POTS)* U1 [4 _, X1 d
Remote Access Server (RAS) Modems
) f$ N& T1 Y2 L ADSL (Assymetric Digital Subscriber Line)4 @. s4 t' I0 z2 i9 `* [5 A% @
Digital Cellular Telephones- B+ }! Y' ?' }/ _$ n l! P
GSM Handset Using SoftFone™ Baseband Processor; x, L; B/ R6 h4 V2 n: O8 j
and Othello™ Radio& O7 Y6 g4 y8 X" i7 M/ a
Analog Cellular Basestations
! D* |& p+ s, [0 E, x Digital Cellular Basestations6 C0 m, W) O; t0 O: N4 i- a, ]8 f2 a
Motor Control
) x$ q% ]8 v. a2 `% z% U Codecs and DSPs in Voiceband and Audio Applications" A7 P- d, I8 i/ u3 F% ?3 K
A Sigma-Delta ADC with Programmable Digital Filter
, L( l% J" \9 R) S# b8 {SECTION 10
, h0 ]: g$ A( P; U) ~6 S: ?% cHARDWARE DESIGN TECHNIQUES( U7 o! V' Y- \( R
Low Voltage Interfaces+ |4 v6 c3 D: b1 o9 o/ ?
Grounding in Mixed Signal Systems
( u5 K( f0 ]. G8 @ Digital Isolation Techniques# O; s L6 P+ s; L7 X& W9 k9 y2 M
Power Supply Noise Reduction and Filtering
2 Y) C9 F- T+ x, m/ @9 A8 w Dealing with High Speed Logic
% w. R9 Y u+ HINDEX文字 |
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发表于 2016-12-1 15:13
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