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ction 1: Getting Started
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This first section is meant to get a user up and running as quickly as possible. It touches
4 e/ v1 q0 N* n$ `! {2 f( Pon multiple topics that are detailed later, and is meant for application and a quick understanding. 2 p b2 U. M* H% I" \. T
That being said, I think all users should look through this section and make sure they understand * m+ ?8 q# j9 o7 v' O, o3 v: t
it.
1 x3 m2 H2 F7 d- E( H The last portion of Getting Started covers analyzing results, which is an integral part of # f$ z! H( u0 ^3 ~
entering constraints. One can't enter core timing or I/O constraints without being able to read the 7 n$ d+ p( s/ U) z! K9 l
analysis reports, so it is recommended to read that section in conjunction with the information at 5 z5 i1 k+ F3 ?5 C
the beginning. 3 a. J4 y: j# e' G1 J6 L
+ i& R! {9 G5 B/ _% gQuartus Setup
/ h( g+ r0 k9 E. h) Q Within Quartus, there are a number of quick steps for setting up your design with
$ g3 ~9 z( ?. c6 N. E* J2 kTimeQuest. These are accessed through the pull-down menu Assignments -> Settings:
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: s" G1 c. v& Z2 |' E7 d4 c1) Along the left panel, select Timing Analysis Settings and select the "Use TimeQuest…" radio 2 [* u& H" d. W- u
button. The Classic Timing Analyzer is the old timing analysis engine, which is not 2 W: [' I) J! F4 u& ]6 W1 ]
recommended for any new designs or architectures, and will eventually become obsolete.
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- G. `% {3 {' l7 C7 s2 u: i" `2 {2 V2) Select TimeQuest Timing Analyzer in the left panel. The screenshot should look like below, y$ t4 j" Y0 [1 h7 c K
whereby the user can add a new SDC file. SDC stands for Synopsys Design Constraint, which is
9 J/ n, i O* U1 Q. D( p4 l: }the format TimeQuest uses, along with many other tools. If no .sdc file exists, we will create it
, Y L; I& ]7 N: Fin the next section. Note that SDC files are analyzed in the order listed, top to bottom.
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