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楼主 |
发表于 2007-12-18 21:50
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The biggest problem with asynchronous resets is that they are asynchronous, both at the
/ p. M4 \4 H. xassertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the, B( N6 v5 i+ Z& v- Q8 X, z/ F
issue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the% S% Y% W H* A! d
output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost./ G7 n$ V0 |% f- u- y/ }, R8 V
Another problem that an asynchronous reset can have, depending on its source, is spurious resets9 a9 M% `2 U1 X
due to noise or glitches on the board or system reset. See section 8.0 for a possible solution to/ p8 [% H/ M9 F" p4 C2 o
reset glitches. If this is a real problem in a system, then one might think that using synchronous' O( d' |$ p( g- Q) U |! W
resets is the solution. A different but similar problem exists for synchronous resets if these# w; T$ V5 o6 R2 C+ t
spurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is
* y" a. {/ |$ @8 z9 V9 o; strue of any data input that violates setup requirements). |
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发表于 2007-12-18 21:19
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