Lattice芯片ICE40UL1K的RGB脚使用问题

liuchengyun · 发表于 2018-1-9 17:48

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在使用Lattice的芯片iCE40UL1K的RGB0、RGB1、RGB2做普通IO使用时，在板子上量不到信号，后加上拉电阻300R可以输出信号，加2K以上的上拉电阻就又量不到信号了，各位用过的路过的大神，有知道咋回事的还请指导一下，个人感觉上拉电阻加300R太费电了，请不吝赐教，谢谢。

超級狗 · 发表于 2018-1-10 07:57

High Current LED Drive I/O Pins
The iCE40 UltraLite family devices offer multiple high current LED drive outputs in each device in the family to allow the iCE40 UltraLite product to drive LED signals directly on mobile applications. There are three outputs on each device that can sink up to 24 mA current. These outputs are open-drain outputs, and provides sinking current to an LED connecting to the positive supply. These three outputs are designed to drive the RBG LEDs, such as the service LED found in a lot of mobile devices. An embedded RGB PWM IP is also offered in the family. This RGB drive current is user programmable from 4 mA to 24 mA, in increments of 4 mA in full current mode or from 2 mA to 12 mA, in increments of 2 mA in half current mode. This output functions as General Purpose I/O with open-drain when the high current drive is not needed.

超級狗 · 发表于 2018-1-10 08:07

User Guide 是這麼說的：

Appendix B. Using RGB and IR Pins as User IO
To use the RGB and IRLED pins as general io user must instantiate the SB_IO_OD primitive, see example below:

module top(a,o1);
input a;
output o1;
wire o1i;
assign o1i = a;
SB_IO_OD OpenDrainInst0
(
.PACKAGEPIN (o1), // User’s Pin signal name
.LATCHINPUTVALUE (), // Latches/holds the Input value
.CLOCKENABLE (), // Clock Enable common to input and // output clock
.INPUTCLK (), // Clock for the input registers
.OUTPUTCLK (), // Clock for the output registers
.OUTPUTENABLE (), // Output Pin Tristate/Enable // control
.DOUT0 (o1i), // Data 0 – out to Pin/Rising clk
// edge
.DOUT1 (), // Data 1 - out to Pin/Falling clk // edge
.DIN0 (), // Data 0 - Pin input/Rising clk
// edge
.DIN1 () // Data 1 – Pin input/Falling clk // edge
);
defparam OpenDrainInst0.PIN_TYPE = 6'b011001;
defparam OpenDrainInst0.NEG_TRIGGER = 1'b0;
endmodule