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楼主 |
发表于 2007-12-18 21:50
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The biggest problem with asynchronous resets is that they are asynchronous, both at the3 P% B( m2 o, p& [9 H
assertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the
8 u8 R% e, D% z; R/ \issue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the3 Q- y0 X6 ~1 t* ?. _' A _! D
output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.
. W) c+ y) z' P1 f) RAnother problem that an asynchronous reset can have, depending on its source, is spurious resets% `7 ` b9 H6 f6 d8 C* {
due to noise or glitches on the board or system reset. See section 8.0 for a possible solution to) Z, A* v7 T1 ^$ i/ r1 B
reset glitches. If this is a real problem in a system, then one might think that using synchronous
0 K; W2 n( b8 L2 hresets is the solution. A different but similar problem exists for synchronous resets if these
2 p3 _8 Y3 Z* j1 ~* g' [spurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is
: q9 [( l$ d; l; Etrue of any data input that violates setup requirements). |
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发表于 2007-12-18 21:19
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