|
|
http://dl.vmall.com/c0fu1auqa80 { n8 l+ d# M& G/ m; y, v
+ ?& D/ Z0 L, H, u: n
# h6 H7 D, b- c8 S/ R
9 N5 e( N6 S$ u. o" W* V& u) aDATE: 02-14-2014 HOTFIX VERSION: 023
" W$ F& a* z' p3 q/ [& ?: }- y$ h===================================================================================================================================
0 N# A0 N+ N, z+ E' b' w. j% U$ gCCRID PRODUCT PRODUCTLEVEL2 TITLE
; u- `4 G h% i===================================================================================================================================( h% l- ~' {3 F/ V0 K" I2 P
1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
5 }6 D8 L: ~- Y: ~! U" x9 a1202715 SPIF OTHER Objects loose module group attribute after Specctra
5 y: Q1 t5 X/ M% R K/ Q$ _( \1203443 ADW LRM LRM takes a long time to launch for the first time
+ j1 o; H' c2 u4 K1207204 CONCEPT_HDL CORE schematic tool crashed during save all/ O) C1 Y: y" Q: I$ K y l) N m
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter9 b8 A4 c9 F! V2 _+ m
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA6 R x, g8 f; x) F
1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side: l3 L- S" B" y. {2 L7 c
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr: K; B- x) i2 P9 u5 H
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.* [) a! [8 P9 W2 O7 ~7 ?3 _
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
: S! x5 B) @1 {8 N0 l1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
" b; U$ V% e/ W& V+ l1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7& M# R8 C4 X2 F4 p3 e) H: A
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's, G2 X$ K4 {( H0 M3 n O
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
. |/ ]5 o: O. P7 C) D" f& W% U/ b1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes/ N& w$ n! O1 J
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form$ i' ?( M& C' K
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
/ {, _3 X' d6 C' H7 m6 R2 L- y1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
- Q7 |3 f' D6 s* V1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.% C! l- H/ r4 e/ r' J3 B& d
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
, u8 p" D7 {# u! g1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol5 n! C0 @% F0 j" ?! M$ v
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
& |, k8 q4 V' d8 q3 T, G' ~" S1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File
8 T3 g2 Y0 r: W: A! D' v# v* q$ i1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
|
/1 
发表于 2014-2-18 16:44
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
楼主
