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$ \" h& d2 ^/ y, A* T1 t! dDATE: 02-07-2014 HOTFIX VERSION: 0228 i4 O" |: J5 Q* @. T
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CCRID PRODUCT PRODUCTLEVEL2 TITLE9 }4 z7 z. G8 l; N( ?: |6 v
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) X5 Q1 v* m$ Z192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes
* Z/ K$ @% Z! \, I9 N% x222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created whenimporting PADS design5 G& R' X6 i. P8 m6 t( {
274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN
: b; l( M/ l' `! D7 F4 f413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes.' q7 ?, |! o) @: y
609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not workcorrectly for MM data.
7 t& y2 t2 d& o0 d666214 CONCEPT_HDL OTHER Option to increase Line thicknessin publishpdf utility2 z. G9 s5 Y: E4 O m. t
738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphicscard
$ j8 X8 y: D# f/ S$ b% r( G/ o982950 CONCEPT_HDL OTHER change the mouse button for thestroke to have same function with in pcb editor( ]8 J+ K. ?" T" n( D+ l4 g2 C, Q
1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (byimporting macro_pin list)2 H8 H0 ~% f+ M$ G7 P
1032678 CIS VIEW_DATABASE_PA View Database Partgives incorrect result in complex design with variants.- n0 R5 Y1 m8 z+ {/ ]
1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardropspresent in design& Q6 V" ~1 m0 l1 ?8 ^# D6 w
1054862 CONCEPT_HDL OTHER Option to increase Linethickness in publishpdf utility
/ F$ |) @& O$ G' X; T1055252 FSP PROCESS Add a synthesis option to target agroup to contiguous or consecutive banks( m8 e9 {5 M+ V
1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC >Spacing the Show Element DRC totals are wrong.
3 j, g: ?* Z- r7 z. t1135020 CIS DESIGN_VARIANT Variant list is showing wrong results forhierarchical designs
. ^% \" ]! N g6 ?. w) Z! [1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly supportpinnumbers on ports
( s1 |0 U7 A* P1 A& C& x, W8 P1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis arelost after closing and opening Constraint Manager.) M+ A4 I' M; U' `1 z
1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pickto options increased to include Pin edge
+ Q3 `' D! U6 E6 M8 O% P" E( Y& B1147961 PSPICE SIMULATOR Simulation produces no output data; `2 ~, G2 M t6 _. U; p
1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translatedcorrectly during pads_in translation
' X7 Z) u# Z5 p7 ?$ g1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology isextracted in 16.3 versus 16.6
$ k; s: M# V" B9 I1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value inVariant View mode# Z1 [. B2 w* M I8 d$ f
1158350 CONCEPT_HDL CORE Need a warning Message whileimporting a 16.3 sub-design in a 16.6 Design
- W, f2 K4 x3 k2 h) E1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move commandsuch that it allows stretching etch using only 45/90 degree segments directly! n; _! Z# H! T. l# o# S6 M
1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the statuswindow does not represent correct colors.
1 |( x0 z4 z; y* r8 o( B1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editorallows user to overwrite the master with no warning1 a0 ]( Z7 ~1 q$ g) {
1172043 SCM OTHER : in pin name causes SCM to crash; A' ~" \5 {' E6 @3 A5 z
1172207 CAPTURE STABILITY Capture crash while adding new partfrom Spreadsheet
6 ?8 _, Z# {) e ^1172743 ADW TDA Allowed character set for thecheck-in comments is too limited0 c1 L' D$ _2 i
1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace" n, v. m2 S; ~# n* t' Q& {
1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about whatcolumns have been ignored by import process2 B1 ~2 H0 y) Z( s
1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATIONproperty can not be set to invisible- [* w" F3 s" X2 B3 M8 w s: {' V. ]
1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attemptingto launch CM
; d1 i O) _. C* c% v7 l1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after thedecimal point of Shape Creation function does not match the Accuracy of BRD
# o. g. K. n! s+ H1179688 PSPICE STABILITY pspice crash for particular HOMEvariable vlaue
/ Z8 w6 S! b" X) C6 a# U3 Z+ A1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbolexport - enable field to add Keywords for data fields to excell cells
2 ]9 m( H0 m2 A6 T/ T$ @1 V1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Streamdata from SiP database.
* T5 {' s% q* E. d) {1180164 F2B BOM BOM csv data format converts toexcel formats
- `) q3 a9 @8 [7 ^- z# J; i1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicatelocation in the comment section) ?* s# @3 i1 z) U; c+ p
1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheetadd option for writing to existing spreadsheet# U2 N$ z9 S8 |6 ]- m1 R- k
1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctlywith RMB-Move Vertex: F* E$ g9 s; o' f/ S7 M
1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to RouteKeepout Spacing" when there should not be one.3 E: X9 K1 R9 c p$ u0 O
1181739 GRE CORE Running Plan > Spatial crashesGRE
! V! S4 g+ j# J& t( p1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-CDRC errors! K9 H k* W5 k% a, s
1182185 SIP_LAYOUT OTHER SiP Layout - Import symbolspreadsheet - suppress Family for the font in the XML spreadsheet
$ h' y" |3 O- F3 Z8 z' ]% }7 h1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol- Enhance ability of spreadsheet exchange to allow for a portion of a full pinmap5 z! d4 Z( [% G1 }+ c( t1 Z
1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not updateafter Z Axis option is turned ON or OFF and Analyze is run.2 a4 o" W! I* c- S: C! E( \
1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotationbefore placement
+ O1 M7 o9 F( T1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask &Nodrc_Sym_Pin_Pastemask to symbol level
( P' l" m$ Q0 r; F, I1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able toselect xda file type when browsing8 y* k) ~7 r# e
1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC3 a: J+ T5 i! d- M- J8 O! S: C
1185946 CONCEPT_HDL CORE Ericsson perfomance testing report5 sept 2013: a" K R/ }1 _% F: K6 W
1187213 FLOWS PROJMGR Unable to lock the directive:backannotate_forward
, M' ^' V. X$ U+ r" D1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check promptserror "SPMHGE-47: Error in call to batch DRC"
, U' u. ]: z0 e. o$ M( r1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error,when symbol overlap sideways at 45 degree.
3 C8 D! L ^% D7 N7 S; `1187723 FSP PROCESS Synthesis can fail depending on componentplacement% m# K+ V) v# p' P* [) Y7 q
1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfacesImport Export and Add Component - include Keyword for NET_GROUP
/ u- a9 H/ _6 \, n# u' ~) o: i1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot runthe CHANGE command in a read only schematic/ S& e* F' N. |9 ~- p
1190927 CONCEPT_HDL CORE Check sheet does not reportshorted signal/power nets if power symbol is connected to a pin% e$ h0 u% B; e6 E& T
1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text blockparameters numbers
7 m3 U, i9 i' [; G% @1 p1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metalshape from file
8 n7 w! Y% b' q( n3 d+ U/ w1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that arelabeled as microvia& Y" F9 F9 a: C1 u8 K1 L4 S
1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is notaccessible from bottom". The component is through hole.
" [ c, W+ b! a |2 R1 O2 h1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S047
, ]/ c/ E) R0 E1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file withno package info
" A, Z+ k- y3 p d5 q1194418 APD IMPORT_DATA issue when doFile->import->netlist-in wizard
2 e. f2 A1 f! W2 Y1195279 F2B PACKAGERXL Ptf files are not being read whenpackaging with Cache+ r- N: R1 D; e/ d6 x$ |
1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools >Module reports2 i) s, M( v5 f% L
1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write PackageOverlay..." to better support longer lists of routing layers& T4 H) \5 ~1 p" K" p
1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of objectfor Spacing Constraint Worksheet
! P; f5 {5 J" Y1197399 CAPTURE OTHER Draw toolbar disappears when usingPrint Preview
. N' i2 c% J+ ]; _6 [1197543 ADW TDA TDO does not correctly showdeleted pages# b/ p1 f# F6 G9 z% T8 \5 I5 g
1198033 CONCEPT_HDL CORE Signals do not get highlightedwhen Show Physical Net Name is option enabled: d( O. J3 r, t& |
1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show thecorrect view in 3D_Viewer when symbols have multiple place_bounds.
9 ~ {" d1 m* r( K# ^: a1198617 CIS GEN_BOM Mech parts are showing with Partreference in CIS BOM
! u) X6 R/ a6 J7 ~0 ~1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying todelete small island on POWER layer.) G# ]% J4 D* P" p0 b
1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outlinewhich is made of lines does not move the board outline in General Edit Mode.' f9 f6 V% f3 T' R& u
1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object tosnap pick
4 g1 [! X3 v3 U# M4 R8 F( L6 t1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip designcreates a .SAV file
- v' P+ ~* \& j' w1201638 CIS PART_MANAGER Part retains previous linking inside thesubgroup
# w Y$ G& |5 U4 ?1 v$ T1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changesresulting imported object
5 {' x# {) p. }6 r2 q& F5 `1202406 SIP_LAYOUT OTHER enable the dynamic display of componentpin names for co-design dies in Sip Layout
" a; l* L- Y" }4 s. g1202431 CONCEPT_HDL PDF The publishpdf -variant optionshould have a "no graphics" option+ b1 y# E0 P3 G
1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal linesegment ... end points.
$ Y3 e5 G# Y+ M3 ]' F* R+ `- @1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to outputinformation for a specific design.
# s5 ]9 \$ \ Y( X8 G, F1204544 F2B DESIGNVARI Variant Editor does not warn on save ifno write permissions are on the file
Q- x% Q$ E+ W* E9 C7 M" p1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDLsyntax
6 ]- ?1 D. ~% [0 J+ i1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part isvisible in 3D viewer only when Etch Top Subclass is enabled4 p0 o% S) U3 a, `
1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and addSkill access I/O driver cell data
' c6 K3 m, Y/ `6 D) F7 U8 G( v* a1206546 CAPTURE ANNOTATE User assigned refdes are resettingwhen 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�& e% p R+ ?. A6 { C _8 g9 ?, A
1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Stepfiles are displayed in the 3D View6 S0 U- K0 G1 d" ~ N7 s4 l
1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus: K; I: W" D* m. \: I* q3 W$ j
1207386 CAPTURE GENERATE_PART Altera pin file not generating the partproperly1 G# F$ v3 s5 `8 `$ W
1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command notworking
4 ~4 B; u" a% {2 h1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pinswith black color
/ I( M& Z; w% w# i1208017 F2B DESIGNVARI sch name is not same when updatingSchematic View while backannotating Variant2 H4 ? A/ U5 I% q; t2 s
1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polarcommand the tool returns 4500.00 for 45 degrees.
% H& O% Q5 t, ^1209769 CONCEPT_HDL CORE Top DCF gate information missing' b0 H# C; e, l! h4 r) t8 r* M
1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box- b( ?6 n1 L0 w* \ y' D
1210442 CONCEPT_HDL INFRA Save design givesERROR(SPCOCN-1995): Non synchronized constraint property found in schematicpage
5 s9 Y5 v* N' |( E1210685 ASI_PI GUI User can't edit padstack inPowerDC-lite4 S6 S8 C$ r7 w0 \" ^
1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seemsnot to be correct" |8 F- Z: m. ?0 R! m
1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file2 h v! c" M2 ~/ K# r- F @* o
1210850 CONCEPT_HDL CORE DE-HDL backannotation crashingafter instantiating specific cell from Ericsson BPc Library
5 J0 {* q6 u7 m V( o1211620 ADW COMPONENT_BROWSE Component BrowserPerformance- O& N" ~1 K9 [4 {! V
1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored tothe highlighted preview.
7 v7 y. Z1 p6 M8 e1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails tosection first contactor pin from column of individual pins
( X- h- K3 z" f3 z7 p p1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose netsentirely.
) i; r3 P" E! ^1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partitiongets connected to shape on the board after importing partition
3 z2 y% w: M$ r/ s/ s4 t1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folderin Spacing Constraints in CM does not automatically select the first column forediting1 t$ w, H( I$ h0 K! T
1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option, D; z0 n& J8 y
1214433 CONCEPT_HDL CORE Genview does not update sym_1 withports added to the schematic
) h! _: q9 V) K. j- z* Q* T( E1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rowsfor drills
) v& R' T }" j9 h1 S# s1214916 SIP_LAYOUT OTHER package design integrity check forvia-pin alignment with fix enabled hangs7 C3 [' v" `+ F4 u. t T
1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error whensimulating extracted net- {/ F& a9 {1 k# N% [+ ]
1216328 CAPTURE STABILITY Capture crash
" ~' B1 a7 d+ n2 u1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.049
% q8 R6 K2 V$ r( i$ |1217450 F2B BOM ERROR 233: Output file path doesnot exist
* | M7 q V/ ]9 [' X1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replacepadstacks that have multiple alphabetic characters in the pin name - AB21-AB377 ^5 \3 E2 w# B6 t; E* Y3 f
1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-473
& ?% U' _) }0 ]' K* E1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available inthe STEP Package Mapping window
" V0 X2 E9 q9 \( @6 o% G* ~5 w2 A1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side partsare placed above the pcb board surface0 M4 C" L* ?& t# a
1219053 PSPICE PROBE PSpice crash with the attachedDesign
* h- r/ y; R8 a' b, g# E/ ?1 h0 C1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable0 l; z j9 J' U* R6 k5 N4 d5 a
1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is taperedfor two layer board1 `% f, ]- e3 p" d; {
1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol()
2 M. J" x7 B* b H h6 J1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview(showhide view command) fails with command not found& b. e8 j& o6 Q0 r+ o# w# ~
1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report forspacing is not synced with the design8 d" h- X" E- e1 }0 q
1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differentialpair
$ [3 c, ~/ K/ j8 }1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importingdata correctly into sip
1 j+ y" ^% M& E# w7 ~, u; f B1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts withsevere convergence issue when coupled vias is enabled.
- e9 V# V4 ]6 m0 l! R" V1221416 ALLEGRO_EDITOR DATABASE strip design for function type
7 V e+ w* S8 p' M( U1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embeddingcomponent
# C) [4 f6 A! l# a; a1222105 CONCEPT_HDL CORE Moving Pins around the edge of aBlock causes the text of the pin to change its text size.- f4 {, }7 _) Z* c0 k, T) |, I
1222124 APD DATABASE Same Net DRC's exhibiting inconsistentbehavior./ R; H& N- R, Y9 G
1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorerafter selecting a netgroup
, \& ~2 Z3 Q4 I# f* y1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top% Q/ X9 b3 F- i v" T4 T3 L
1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message whenusing the BGA generator with a long BGA name.
1 N! o8 n; L: M* P( {9 p! O h/ c1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying torefresh symbol4 G- s, j8 n; Q) l, J
1223932 CONCEPT_HDL CORE DEHDL block desend does not find1st page if its not page1
* } C$ Q" s6 N" m4 k c4 N1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name inSetup/Hold Worksheet under Timing in CM.
: i" S8 g& o9 p% b+ \% i, T3 l4 r1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6officially supported?
; }; E2 h' M* b L: ~, x M' p1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizessymbol outline to maximum height again) G y: A9 J& r' w1 p
1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS mapscorrectly in constraints manager for front end but not in back end
- i7 L8 _/ Y- }$ E8 i+ |1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filterconfig file eventhough it is created in same session and stored in parent folder6 x0 W+ { e8 W. X: f2 `$ w
1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDNAnalysis with XL and GXL
8 W. ]/ b7 o6 A& f3 H5 N1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheetenhance sort to be a natural method per Jedec according to customer |
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发表于 2014-2-10 15:09
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