|
EDA365欢迎您!
您需要 登录 才可以下载或查看,没有帐号?注册
x
本帖最后由 zgyzgy 于 2015-10-10 11:35 编辑 9 I; B: V0 ~5 t1 J8 s3 f: a0 p8 m
+ A5 F, a% b/ m% u/ X v. H昨天刚出来的。。。。。。
: M) d2 b1 h6 _. C. F1 r: l3 m8 Z% d9 c
DATE: 09-31-2015 HOTFIX VERSION: 059( {' ^& Y. [# k) {) f
===================================================================================================================================
_7 s/ Z9 Z6 PCCRID PRODUCT PRODUCTLEVEL2 TITLE* B- ~$ O8 G* E/ r
===================================================================================================================================6 X: e' V, H0 W6 |3 e2 _( S+ ]
1181942 SIP_LAYOUT ASSY_RULE_CHECK ADRC reports different results from the spacing set-up
+ c4 N3 W0 i3 B i9 i1328452 ALLEGRO_EDITOR INTERACTIV When changing the shape type, Right-click - Next does not work for subsequent changes
& Q) _. k0 t+ T3 y: O1441502 GRE IFP_INTERACTIVE Design partition cannot be imported." `7 u) V J5 q j
1457920 SIP_LAYOUT OTHER Wire Bond Import is not working correctly with discrete parts
* f+ }/ b! A* Z+ |" K$ S* ~1464865 CONCEPT_HDL CONSTRAINT_MGR For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM
0 h6 \0 O( x' m7 |/ O% O- C S1467365 ALLEGRO_EDITOR OTHER Cadence cshrc for LINUX has an extra space in it.
5 N; I, Y2 g: b; d4 v" B% [: [1473744 ALLEGRO_EDITOR INTERACTIV The 'Chamfer' function does not work correctly if the second Trim Segment value is specified instead of the first.
& F, B8 k' B5 I; T1475599 SIP_LAYOUT SYMB_EDIT_APPMOD Refresh co-design die of an enlarged die is not placed correctly7 m H$ e: E4 e
1476284 CONSTRAINT_MGR OTHER Changes with Tpoint pairing not being propagated to the brd file
" b8 i0 x! h' w$ o$ B5 Z1476528 ORBITIO ALLEGRO_SIP_IF While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown+ p; A" i0 o% ], |9 o
1476855 ALLEGRO_EDITOR DATABASE Trying to import Netlist, getting SPMHNI-194 error+ n; S- r# d- b( v4 Q- a( N
1476920 CONCEPT_HDL OTHER Genview consistently fails in some indeterminant manner.
8 X" M; E+ _% Z+ U# m1478111 F2B DESIGNVARI Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release
6 ?/ ]( d% I5 F9 z6 k& \1478225 SIP_LAYOUT DIE_EDITOR IOP incorrectly rotates pins at a co-design die
* M* r) t4 K1 x. N& D( S7 a& p1478465 SIP_LAYOUT WIREBOND Ability to set default bond wire option to on for wirebond import/export commands* l8 J0 L0 K! Y5 }
1478994 SIP_LAYOUT SKILL axlUIMenuChange does not work on Linux' b/ X. G5 t" Y4 y/ J/ G5 [- D
1479023 CONSTRAINT_MGR OTHER The cmDiff reports different data when files are reversed in UI4 t" Z' h; l, @
1479785 ORBITIO ALLEGRO_SIP_IF brd file does not get loaded in OrbitIO
# X( i; @; ` d' E1480367 SIG_INTEGRITY OTHER Differential pair extraction SKILL error, 'parseString: argument #1 should be either a string or a symbol'% h. j. o* i, i' ^* e
1480538 SIP_LAYOUT DIE_EDITOR CTE compensation is limited to 3 decimal places, can that be increased2 v" [7 ?5 W% t( Z" k d8 s, N
1481109 APD MANUFACTURING control Package Design Integrity for snapping the via to pin! y8 I( m, w6 `+ u
1482771 SIP_LAYOUT WIREBOND Fingers and wires cross when moving the guide path a* A; [5 p# M+ H: e* W/ Q
/ U0 K8 @- }, |3 W3 Z" u: Z% R正在下载文件中,稍后分享链接。。。。。。
. Z9 Q' k4 n9 }- E& M! M# a8 h4 Q) f. T/ @$ B! j4 D; ?2 N
6 R) {! |8 }* X4 l0 a W2 K8 D& J6 s% O) T. x9 p
5 q+ g i) A3 T N" a. ?: n2 G) `! {9 N1 q& d6 O7 ^) r3 O
+ D, r# U- Q; W) G
- P: b+ K: G; X
, s: D8 a1 H. M5 E) l' c0 m3 e1 s* J" D- n2 u& y" G# S' ~2 j
http://pan.baidu.com/s/1gdnouNx
$ {) G% c$ W( ], b0 X
9 D: L9 F6 M$ b- j) A
~6 c# U r9 ^0 b) `, p2 c7 P" [1 f0 I/ c" J5 L* n' r
" L( P: P' u P2 T
3 [9 q* j) ^$ s. G$ `; A' i [1 p# \( \9 `8 }/ Q
|
评分
-
查看全部评分
|