|
|
本帖最后由 stupid 于 2013-4-30 23:17 编辑
1 \3 w' s1 T( D* \% p8 T+ s$ n
/ {5 B9 Z7 `7 V5 p某一天，一个叫马克的人发起了帖子，采用了滚动刷屏的方法，4个帖子，一个内容：招人
0 q! K6 @ T# B6 }1 }( F) d( |$ S4 W6 [8 K
首帖Date: Mon, 7 Jan 2013 17:36:56 +0000
# }! ]$ b8 M" X# j0 M2贴 Date: Fri, 15 Feb 2013 00:22:29 +0000. L/ P, d! i7 ^) ]& F2 P8 |
3贴 Date: Thu, 14 Mar 2013 04:49:58 +0000; I1 ~1 r0 V: {) Y3 ?
4贴Date: Thu, 25 Apr 2013 18:37:34 +0000
8 C7 {7 x/ ~5 a) }5 f7 a) D+ t8 A# S3 o6 @( o, o% ~
My Team is looking for a Senior Staff Engineer(Backplane Architect)/Principle
, G) o' y! }3 V4 ^: z+ w4 kEngineer;$ T7 |* @6 B, u6 @) ~/ i1 ~
Responsibilities/Description;/ X3 a& n a5 ~5 `
Responsible for providing the backplane architecture and 10G+ High Speed SI
2 z* ^ K. s+ n R& }/ Dsolutions for Next Generation telecommunications equipment in the router,0 y' t4 x$ z ~/ ]8 P$ K" ]
switch and transmission product lines to meet system design requirements.
! [! f# a! _7 x; v4 E6 q* QExperience in co-designing of ASIC, Package, PCB and System interconnects1 ?. T, @2 a2 r4 f4 l* e- g
desired. including:; f9 @" ?: @" A' A# B
+ N: [: _5 S) a* m- Design and analysis of multi-gigabit serial links for Backplane and; Z/ f* `. V5 \
chip-to-chip interfaces meeting CEI, XFI, XLAUI, SFI, 10Gbase-KR, PCIe, and
* o: @( C1 t4 c, j: U$ u other standards., Z( x) G5 W/ t @4 \* z
- Familiar with ASIC, Hardware, interconnect teams to evaluate design
3 R# f# J: s* x$ H; m tradeoffs and optimize design performance / risk / cost /manufacturability.4 Z; P' h% l; m2 ~; ?
- To evaluate package designs, characterization of SerDes, and design' U* \& Z- Q- j* B4 e5 E
experiments to do the same.
. d$ n8 Y) r s9 c6 w- Modeling of electromagnetic 3-D structures.
: X5 l) t( `# n- Modeling and analyzing power delivery networks (PDN).
8 |' L$ q. R- S; N- Familiar with memory technologies such as DDR2/DDR3 is preferred.
" V/ T6 c# u* r
$ f/ B2 k: `( Y+ ZQualifications/Requirements:6 r) l8 P. B- a" Q
% U/ }- w4 B: ~. q- L; H3 F2 U
- Performing physical measurements to collect data for design
0 `8 W0 d) F+ M1 P' |2 p) h validation and simulation correlations.
5 A7 a! m9 y8 U) e; B+ V. |- Knowledgeable in using most major SI/PI tools: HFSS, CST, HSPICE,. I& @1 O+ x5 o: Y" R6 ^* _. n8 U
Sigrity Tools, StatEye, ADS, Matlab, Cadence Allegro and APD, HSPICE, and4 [3 T0 W6 K( \+ J& L
other tools.4 w, E$ W+ P4 A" r6 p1 g& p$ J
- Experience in correlating simulation results with lab measurements
+ ?! g1 O+ F w, G, T using oscilloscopes, TDRs, VNAs, BertScope is a plus. Must be self" X' |$ [: L' [ h& `5 [' v9 l" q& @
motivated with strong communication and teamwork skills.6 c, s. q& p. n* ~+ \
- The working experience in Core router or Edge router similar product
_* M; o( m! Y! j6 f- d in large telecomm infrastructure company.1 O: a/ |; h; i4 @
A MSEE, or a PhD is preferred, with 10years of experience.
5 K7 O' x: {: K% i" r
, H J; c, R" G: l& O! m% SSome portion of time will be spent in Shenzhen working with the HQ SI team.
3 x+ y+ k# p1 I0 ]) _) S9 R% TTravel will be about 30-60% to China.5 y/ [$ J/ o1 Z
3 E) g5 w& A$ ^2 q- f& C0 Y% `7 nPlease contact mark.apton@xxxxxxxxxx
) S& _5 s8 g. z4 b3 N2 T( x2 k+ l1 ?2 H/ s# V4 p: Y( R
插个广告，有符合以上条件，又愿意在深圳工作的人速速联系我 dbm@chinafastprint.com |
|
/1 
发表于 2013-4-26 22:19
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
发表于 2013-4-30 23:10