生成网表时，错误如下：6 ^; ~5 ]3 M6 P9 v3 x p
Loading... E:\CadenceWork\毕业设计\IF\rev10\allegro/pstchip.dat 1 t2 j- s4 R- {6 g3 S% F; xLoading... E:\CadenceWork\毕业设计\IF\rev10\allegro/pstchip.dat6 f* S8 D3 m D, `! V. s+ G9 E$ M% }
Loading... E:\CadenceWork\毕业设计\IF\rev10\allegro/pstxprt.dat # M) O5 u O3 t; S#38 DDB_ERROR: Terminating character ':' not found on line 965.2 S' I9 D0 n: c
DDB_INFO: File E:\CadenceWork\毕业设计\IF\rev10\allegro/pstxprt.dat not loaded. ; ]8 Y$ z* M. J" xError: Line 965 in file E:\CadenceWork\毕业设计\IF\rev10\allegro/pstxprt.dat:* a2 v. k! `% f# E4 V
Error loading the parts list file * Q9 g/ C! k" u/ X3 p. H& W5 [- {
Detected in function: ddbLoadPstXFiles , L' A4 |5 R; L: b f
#44 Error [ALG0036] Unable to read logical netlist data.& O2 R! z- Z2 [* m
Exiting... "C:\Cadence\SPB_15.7\tools\capture\pstswp.exe" -pst -d "E:\CadenceWork\毕业设计\IF\rev10\rev10.dsn" -n "E:\CadenceWork\毕业设计\IF\rev10\allegro" -c "C:\Cadence\SPB_15.7\tools\capture\allegro.cfg" -v 3 -j "CB Footprint"8 t y5 p y0 R0 c# z6 n
问题已经解决了，是原件的编号出现了非法字符 空格，为了避免大家与我犯同样的错误，特写出错误原因及查找：, @/ A7 n' ~1 Z! H, @6 T' _8 V
1：首先在capture帮助文档中查出ALG0036错误代码的解释及原因，如下 & Z( b! {8 x) Y2 HThere was an error encountered while reading PST*.DAT files. This error is probably caused by invalid characters in the PST*.DAT files. You have probably modified your netlist files since importing logic to PCB Editor. Remember that even things like deleting a net that doesn't have a net alias and then re-drawing it will result in a new net name since net names are auto generated. W. p5 U5 U+ \, H" ^) E
2：查找对应的错误文件pstxprt.dat中965行，知道错误的元件编号（此处为R24 RCK02A1） " B( B. _- J8 O! ]7 e3：查找原理图中对应的元件，发现元件编号为R24 RCK02A1，出现了非法字符空格，因此将元件编号修改为R246 ?0 p8 }# Y! g" J/ |
4：重新生成网表，问题解决了
/1 
发表于 2010-8-20 18:22
CB Footprint"8 t y5 p y0 R0 c# z6 n
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
楼主
