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EDA365电子工程师网»技术社区 › 电子技术社区 › SI仿真资料与模型 › PCB Designer’s si guide
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PCB Designer’s si guide

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发表于 2008-5-26 11:07 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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PCB Designer's SI GUIDETable of Content ( {' L1 d3 j, `* {# F; z  B
Basics of SI___________________________________________________________________5
# Z$ H9 h0 U9 y' D0 R+ u1.1 When Speed is important? _____________________________________________5 7 @0 h0 T% m1 k9 H8 E5 _9 E
1.1.1 Acceptable Voltage and timing values ________________________________5
9 U# c& d' k4 t; s1.2 Signal Integrity ______________________________________________________5
! Z2 F! f6 l4 K( Y, `/ z6 E/ W$ Z1.2.1 Waveform Voltage Accuracy _______________________________________5
( p1 g: ]& K: y' x1.2.2 Timing_________________________________________________________5 6 v& s/ b$ Y! y! Q" R+ c0 J3 J
1.3 Speed of currently used logic families ____________________________________5 2 x" g! V7 B8 [! x
1.3.1 Transition Electrical Length (TEL) __________________________________6 ( x4 Y( G$ Y6 j
1.3.2 Critical length ___________________________________________________6 0 ~* z* P0 V0 q! H& Z1 {
1.3.3 What is Transmission Line? ________________________________________6
! J5 b9 W# X, K1.3.4 What is moving in a Transmission line?_______________________________6
  S% p6 U3 b3 d2 {1.3.5 Power Plane Definition____________________________________________6
4 n2 g* T- j0 D1 o. S) P1.3.6 The concept of Ground ____________________________________________7
/ J% D  ]1 w0 H- ?& x% z- v" _1.4 STRIPLINE circuit with Electromagnetic field _____________________________7 4 W! Q9 T. M1 O  R( i; G. A  M* E
1.5 RLC Transmission Line Model _________________________________________8 2 ]0 G+ N9 E) }& a- B8 t( o
1.5.1 What is Impedance? ______________________________________________8
% Z( X9 w% z7 v" [1.5.2 A Practical impedance equation for microstrip _________________________8 % p; J" j, W: `  ?3 C( x
1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10

* y+ j' Y+ C; k3 t( z) w) \2.1.1 Summary______________________________________________________10 ( S7 I) z  ]/ `1 Q& l& Y
2.2 Examples of dynamic interfacing problems _______________________________10 0 v2 _9 b! R$ w" {2 }7 a
2.3 IC Technology and Signal Integrity _____________________________________12 ! Q. x& m, u$ h1 _& h5 q$ W
2.4 Speed and distance __________________________________________________14 ( Y, {( a6 r; k: y* P4 u) ]- \. c% [
2.5 Digital signals: Static interfacing _______________________________________15   G) c. v/ N' j8 ^3 R0 C
2.6 Digital signals: Dynamic interfacing ____________________________________16
3 I: K4 x6 E# u% e/ _& x9 `2.7 Review questions ___________________________________________________18
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3 Interconnection Models____________________________________________________20
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3.1 Summary__________________________________________________________20 9 d' Z1 V* r1 F* W% R
3.2 Reference model for interconnection analysis _____________________________20
' T' ~3 r8 T. b5 M: b0 o% h3.3 Receiver model_____________________________________________________21 2 G8 w) z' w9 K" G
3.4 RC interconnection model ____________________________________________23 - c6 d- D4 Z- m. l  b0 z3 v7 G
3.5 Parameters of the interconnection ______________________________________25
9 }5 ]+ K5 v& |6 p* a3.6 Refined models _____________________________________________________26 4 o& q' K$ r/ j" {
3.7 Review question ____________________________________________________28
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4 Transmission Line Models _________________________________________________31
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4.1 Summary__________________________________________________________31 9 L# W) t0 h1 k: \
4.2 Transmission line models _____________________________________________31 1 s; O- C2 s" b' W
4.3 Loss-less transmission lines ___________________________________________32   a$ B, L$ b+ M' _1 d9 `
4.4 Critical Length _____________________________________________________34 8 s5 j. h7 A! B; t
4.5 Reference transmission line model______________________________________35
1 d1 m0 D, a& a+ u  Z& M, n4.6 Line driving _______________________________________________________36 $ O; w# C  n+ S( {5 A3 i
4.7 Propagation and reflected waves _______________________________________37 , R6 Z& D4 M; O+ j4 r% B
4.8 A sample system____________________________________________________39
: G; k5 F8 M0 \4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata
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5 Analysis techniques _______________________________________________________45

, g! p5 d8 t+ r1 ]5.1 Summary__________________________________________________________45
0 i( @0 X+ _8 r& D8 X  s5.2 Transmission time and skew___________________________________________45 ; C; ]  o6 }: R+ c+ N( z4 T' A% ?; ~
5.3 Effects of termination resistance _______________________________________46 7 A- M! _8 e9 g, M2 \0 H
5.4 Lattice diagram _____________________________________________________48
* k1 `& R3 e) j. x. m8 M) o! \5.5 Examples of Real Lines ______________________________________________49 + U0 ^, t6 ]) }7 o( I' c* V" ^
5.6 Simulation code ____________________________________________________51
) f4 W( V" q- k3 Z6 O( O5.7 Examples of results__________________________________________________54
1 W' U/ \  X, y6 \; f' h0 G& a, @; m5 B5.8 Review questions ___________________________________________________55
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6 Design guide for interconnection ____________________________________________57

: N' d0 a, b& Z& G7 ^6.1 Summary__________________________________________________________57
& U$ o; d/ y/ T* W5 E# u6.2 Incident wave switching ______________________________________________57
4 p/ c* w3 _( Z+ F0 c5 H' D6.3 Effects of capacitive loading __________________________________________58 & {7 @1 k1 x* D
6.4 Termination circuits _________________________________________________59 : |0 \) m4 M. h' z, M3 @
6.4.1 Passive termination______________________________________________60 3 j) l$ G: P5 b% E5 R  C- P& V
6.4.2 Low power termination___________________________________________61 5 L: Z1 T, B4 [
6.4.3 Active low power termination circuit. _______________________________61 5 t0 f/ @1 A: B$ ?: C/ `
6.5 Driving point-to-point lines ___________________________________________62 ) H* M( |9 X( f7 {4 F0 {
6.6 Driving bused lines __________________________________________________64 3 y6 j- d0 P& R3 [+ ]2 z7 v
6.7 Design guidelines ___________________________________________________67
! D3 |& Q! y' T, b6.8 Review questions ___________________________________________________67

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Signal Integrity in Digital Circuits ___________________________________________70 % q+ z) P) Q7 ~. P( L
7.1 Crosstalk __________________________________________________________70 1 m* D6 T' K4 y
7.1.1 Summary______________________________________________________70
) b/ w! R: D9 |# ]0 G. g+ y7.2 Examples of signal integrity problems ___________________________________70 8 p0 E2 f# Y0 g( Y. a3 w
7.3 Simplified Model for Crosstalk Analysis _________________________________71
" b& [4 ~: `! {( e7 E4 P, L- q1 [7.4 Forward and backward crosstalk _______________________________________74 % C9 x9 q2 j) Q! ~3 @
7.5 Examples__________________________________________________________76
4 @: U0 W. I& P  h7.6 Near-end and Far-end crosstalk ________________________________________80 4 s7 [* [: J1 y) ]2 ]
7.7 Review questions ___________________________________________________81
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8 Design Guide to Handle Crosstalk ___________________________________________85
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8.1 Summary__________________________________________________________85 2 S6 k8 @! {' O; W
8.2 Effects of Crosstalk __________________________________________________85 + u, C8 Y  A1 X7 M! J/ V
8.3 Passive countermeasures _____________________________________________86
- o; W% Y( @# p, Y% `0 g- D3 b8.4 Active Control of Crosstalk ___________________________________________92
$ X# i7 ^  \% N! }: n# e8.5 Review questions ___________________________________________________94
# `9 I. }: @5 `
9 Ground Bounce and Switching Noise_________________________________________97

1 v! t/ G7 Y6 `5 m8 n; x$ Y8 O$ R9.1 Summary__________________________________________________________97 " `1 O  d6 Y8 O$ n: i+ t, }3 U; |
9.2 The totem pole Current Spike__________________________________________97 ) `! J. {' _# X
9.3 Current flow in the output capacitance __________________________________100 7 y3 G' q$ U/ d& [6 ^. S( A
9.4 Total Ground Bounce _______________________________________________100 1 p8 G  s2 k; S
9.5 Review questions __________________________________________________105 % r6 R5 _0 ]. f& b2 R3 h" L0 o" E
10 Design Guide for Ground & Power Distribution _____________________________107
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10.1 Summary_________________________________________________________107
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PCB Designer’s SI Guide Page 3 Venkata
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10.2 Decoupling Capacitors ______________________________________________107 , i7 S; }* K; ~+ L  D$ N/ t  l  l+ |
10.3 Placement of bypass Capacitors _______________________________________113
$ s+ i  s* |+ v) U9 V! A10.4 Ground and power distribution________________________________________114
1 ]4 K2 ~7 Z7 z' [- d4 L6 ]6 j10.5 Clock distribution __________________________________________________115
% m# x) X! Q7 }8 b( a10.6 Review Questions __________________________________________________118 0 a% n/ k' Z. e4 x. Q
11 Laboratory Experience _________________________________________________120 / O( m8 V2 T( [+ \% r- l7 R
11.1 Summary_________________________________________________________120
/ `$ b1 B8 W% }3 I  ]* D11.2 Aim of the experience_______________________________________________120
" B$ {0 Y2 t: D/ \. ]* {11.3 Generator Parameters _______________________________________________122 ! }! {' j$ v  |# `
11.4 Cable Parameters __________________________________________________123
. t+ X2 @) e1 U+ w  [8 X11.5 Mismatch at driver and at termination __________________________________124
6 o. H/ R# ?$ C: B& o3 m11.6 Capacitive Load ___________________________________________________125 $ B- Z' _, ?" n6 @9 ~5 Q
11.7 7. Time-domain reflectometer ________________________________________127
) E/ x7 {3 _/ f- {" E& g' G11.8 Driving the line with logic devices _____________________________________128 , P6 b& Z) I* p6 h' U5 N
12 SI Analysis Strategy____________________________________________________133
# E. `3 F# K- V- i$ C( w12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
+ f3 @% ]( x6 w12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133 ) k% w$ C3 v0 [7 c( a4 a
12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
- J8 L" X) B* P4 a0 F12.3 SOLUTION SPACE ANALYSIS _____________________________________135 . k/ r) x4 n7 G" U' G# v% k5 y2 a5 W
12.3.1
$ r. |, r* {2 hSTEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135 - @# j& C# H/ J# z  ]
12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135 ( B" a) d: J1 v
12.3.3  L; M% V' b$ L# Y$ Q* P& `/ h
STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
, a3 [+ p5 z; G6 b12.3.4
% s1 D+ i0 [  l0 T8 v$ mSTEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136 ; {2 B& f. y7 S: k7 P" J! N; S$ w
12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136 ; r6 h; m5 j8 S2 }0 O) }
12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137 $ w  m& L% a% L$ V2 _+ H
12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137 8 B# v) q! ^, A
12.3.8
' u- F% v( U) U/ LSTEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137 + ]# {' O: p/ O
12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138 ( H4 W; p; F6 A1 E4 Y. A
12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
# g  Q* W7 n7 S8 N" h* k12.4 CONCLUSION____________________________________________________139 : B9 f" \5 E3 Y- }: R1 d$ C% O
13 Glossary _____________________________________________________________141 9 ^1 Y" b% ]6 j- t/ |3 ?
PCB Designer’s SI Guide Page 4Venkata
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