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![]() PCB Designer's SI GUIDETable of Content ( s; o" `5 ^$ u- }1 W) {
Basics of SI___________________________________________________________________5 4 L: F! B+ P6 L- U
1.1 When Speed is important? _____________________________________________5
+ [; l) N! T! b1.1.1 Acceptable Voltage and timing values ________________________________5 ; i9 |; t( d7 \% h8 Y5 {" C
1.2 Signal Integrity ______________________________________________________5
( ?/ X. u7 N& x2 i1.2.1 Waveform Voltage Accuracy _______________________________________5
0 Z" r" d) \- }! G" J1.2.2 Timing_________________________________________________________5
/ L( U& l- {, Y1.3 Speed of currently used logic families ____________________________________5 " q2 M: l# m( ]) f5 s; l5 D4 W7 n1 r
1.3.1 Transition Electrical Length (TEL) __________________________________6 * B0 A4 S$ ]7 ~2 t% ^
1.3.2 Critical length ___________________________________________________6 ) Y7 G' F3 J- i3 R* e3 e
1.3.3 What is Transmission Line? ________________________________________6
8 o j& ]: y: o. @1.3.4 What is moving in a Transmission line?_______________________________6
* g# m* W$ o6 j9 G2 d6 b1.3.5 Power Plane Definition____________________________________________6 % J: a4 m1 j7 E8 P# u
1.3.6 The concept of Ground ____________________________________________7
, o5 _& f8 u7 v5 f7 O! j- L1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
" e# c& I& B3 k5 b, B1.5 RLC Transmission Line Model _________________________________________8
4 O( o3 t( l5 D1.5.1 What is Impedance? ______________________________________________8 3 N& E1 U( o# D9 p
1.5.2 A Practical impedance equation for microstrip _________________________8
) |0 Z9 }' g0 B" U1.5.3 What is relative dielectric constant Er? _______________________________9
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& w% K7 `# ~+ D( r1 g: K( I* k- N2 Interconnections for High Speed Digital Circuits _______________________________10 2 ], F/ ^: B2 z' \6 U9 q1 r# V+ p
2.1.1 Summary______________________________________________________10 2 ]& N% n5 X/ z; C4 H c6 b
2.2 Examples of dynamic interfacing problems _______________________________10
, Y% H5 ?0 r: J) |+ S% J2.3 IC Technology and Signal Integrity _____________________________________12
; G7 F: h }" g2.4 Speed and distance __________________________________________________14
" B, ]; w, ]8 n$ f2.5 Digital signals: Static interfacing _______________________________________15 $ p. U ~% j# ^, b1 e$ Z
2.6 Digital signals: Dynamic interfacing ____________________________________16 ) Y! f7 q! A+ i/ G" R5 J9 q. y; ?
2.7 Review questions ___________________________________________________18 6 R, h" R8 R" i
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3 Interconnection Models____________________________________________________20 , C! Q0 D' x2 Z
3.1 Summary__________________________________________________________20
4 ?; v6 R. B! d; K; M- e# {4 p8 B3.2 Reference model for interconnection analysis _____________________________20 8 r1 u( ~" A q9 Z0 ]( o
3.3 Receiver model_____________________________________________________21 : M0 C& I0 U, S# O, M! i
3.4 RC interconnection model ____________________________________________23 1 Z' M1 o! V: k, j4 n7 I7 y
3.5 Parameters of the interconnection ______________________________________25
+ X; H5 n2 O6 H, K" c3.6 Refined models _____________________________________________________26
5 ^3 p7 T/ P/ z4 M: A, d3.7 Review question ____________________________________________________28
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4 Transmission Line Models _________________________________________________31
4 C+ u$ h, L4 o4.1 Summary__________________________________________________________31
' A1 n4 b: H( J% S; N; o! E4.2 Transmission line models _____________________________________________31 9 t% d9 i( d ?" q
4.3 Loss-less transmission lines ___________________________________________32 1 }* {) |9 l2 V- v
4.4 Critical Length _____________________________________________________34
% F& O" r$ T% F: _/ b* {4.5 Reference transmission line model______________________________________35 . t( A* \6 r( F' h, b3 a
4.6 Line driving _______________________________________________________36 - @+ o3 ^- Q6 v! s7 q
4.7 Propagation and reflected waves _______________________________________37 ! C: S1 T& R. X
4.8 A sample system____________________________________________________39 , T7 A- e! O$ R; o. E4 G8 F" c
4.9 Review questions ___________________________________________________42 , h% ?) V+ [' w$ `
PCB Designer’s SI Guide Page 2 Venkata
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; z% ]* V$ F4 W4 g5 Z/ m3 |, t5 Analysis techniques _______________________________________________________45 ) @7 k+ L" {4 N9 A! A4 d3 g
5.1 Summary__________________________________________________________45
* V. |! J7 I" |5.2 Transmission time and skew___________________________________________45
- J9 Q5 A6 ]7 J; X1 {' \' p5.3 Effects of termination resistance _______________________________________46
5 S; _+ b% r( |: x5 B# F& q* r U5.4 Lattice diagram _____________________________________________________48 $ u6 h2 y1 H9 w: ^, P$ m& H
5.5 Examples of Real Lines ______________________________________________49
$ ^+ F: {+ Y; u8 v' P5.6 Simulation code ____________________________________________________51
8 `0 v! m( ~1 S6 c; Q4 X& ]) Z5.7 Examples of results__________________________________________________54 2 M. l% [7 X3 m9 u
5.8 Review questions ___________________________________________________55
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6 ^' Z* n- W7 t& j0 k6 Design guide for interconnection ____________________________________________57
' D: Z( k) |2 ]% E6 |6 P6.1 Summary__________________________________________________________57 & n- v. a4 L; V; F6 C4 s1 I
6.2 Incident wave switching ______________________________________________57
3 J: \% `- f1 v# y1 c6 b8 q6.3 Effects of capacitive loading __________________________________________58 4 u5 b3 w. g/ U9 [+ o% ]: D
6.4 Termination circuits _________________________________________________59 1 H9 }2 x3 G# S1 J+ k7 o8 q6 ?) g
6.4.1 Passive termination______________________________________________60
3 `6 d+ n; @: M% S; q9 v9 @1 ?6.4.2 Low power termination___________________________________________61
& N' h- j" p( y0 H! t% k( S& Y6.4.3 Active low power termination circuit. _______________________________61
% O1 n+ H' u+ W: f# c/ B6.5 Driving point-to-point lines ___________________________________________62 ; F6 O! T' _& M0 x* S
6.6 Driving bused lines __________________________________________________64
% v; c- B2 F: F3 V2 T% a6.7 Design guidelines ___________________________________________________67
3 [6 S6 f6 m3 x) f1 X6.8 Review questions ___________________________________________________67 | 
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发表于 2008-5-26 11:07
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