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大家好，以前用AD6,PADS, 与在用SPB16.2,很不习惯呀。
- A" n3 v; `, h 在做完原理图，DRC检查没有错误后，生成网表时，出现：& S; Q E% N7 R+ a
#248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'. Each section must have at least one non-common pin.
* n" U. y6 q/ T, ~% c; o Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.& A0 I% k$ R& n. w1 a
我检查了原理图SYMBOL和PCB封装，也换另外的PCB封装试了试，错误依旧。: P. q4 _# A9 w" W
大家帮我看看，是什么原因呀。
" `; y" {1 J9 y 我在画原理图时还碰到其它的问题：3 |4 _' U5 u. q) ~+ u
1：元件编号如电阻电容之后，总自动出现一个A或是B, 如：R120A ; G# @" s$ U; ?, q+ g
2: 在COPY一个元件到另外一个地方去时，本应每COPY一次编号都自动增加，可现在是每COPY两次，编号才自动增加一次。5 d! z- b4 F/ [/ s( g7 n7 [
原理图工程我加在附件里了，大家可以打开F3文件帮我看看。
( j, Z0 ]3 y, u( Y" _$ z 为方便大家检查，我把生成网有的出错贴在下面了：
x8 B* L$ Q& V; y. d ********************************************************************************4 l& A6 O! d0 B. _- Q: s
Design Name:+ K6 p5 V9 ^2 D1 l! q
E:\Hi3515FJ_CADENCE\hi3515fj.dsn: I- N; D @4 }2 V
Netlist Directory:
8 A" B- J7 J' W) ^0 v1 E4 t0 QE:\HI3515FJ_CADENCE\NETLIST
) M3 J3 l$ x( G7 mConfiguration File:3 q, i$ e+ e: R2 `
D:\Candence\SPB16.2\tools\capture\allegro.cfg! V- v8 P7 f5 n9 D5 X
Spawning... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
3 t5 n1 W* r. z#1 Warning [ALG0016] Part Name "PHONE JACK-4_0_PHONEJACT_4_PHONE JACK-4" is renamed to "PHONE JACK-4_0_PHONEJACT_4_PHON".
. u, L" A6 N7 p3 N7 h' t8 h! ?$ ~#2 Warning [ALG0016] Part Name "SN74CBT16214_0_SOP56-20-250-550_SN74CBT16214C" is renamed to "SN74CBT16214_0_SOP56-20-250-550".
7 K2 e0 t; L; m3 \) QScanning netlist files ...
* O7 O6 `4 h. z, E: X' x( ULoading... E:\HI3515FJ_CADENCE\NETLIST/pstchip.dat
8 @2 K' f7 m* E: m+ j#248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'. Each section must have at least one non-common pin.
* @4 N* ]1 J9 m. Z/ @7 h Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.
- N. I% C' {+ i6 D q/ Q ERROR(SPCODD-47): File E:/HI3515FJ_CADENCE/NETLIST/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again.
* \9 a# r1 \, j3 _#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schema
6 V, G b1 d! @9 Y9 D0 W9 vtic and rerun packaging.
/ h3 h8 d; J0 Y2 H5 k) }#3 Error [ALG0036] Unable to read logical netlist data.
! J. g! w7 n4 \! LExiting... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"% {0 V3 o" Z1 O
# W" B; s# B7 t4 `: B*** Done *** |
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发表于 2011-6-12 12:00
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