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DATE: 05-14-2010 HOTFIX VERSION: 0086 W* s4 n6 [, p1 o
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CCRID PRODUCT PRODUCTLEVEL2 TITLE6 X p/ r- E& U
===================================================================================================================================
2 @& M# S3 ~- H4 w% K697699 CONCEPT_HDL HDLDIRECT SCM Verilog output contains the line 揹efparam <instance number>.SIZE
# g3 K2 C" T& {0 n# G* m5 `/ [% _( _734169 ALLEGRO_EDITOR PLACEMENT Wildcard asterisk character giving "illegal char(s) in refdes entry." error in quickplace.
" r( F5 [6 L& S# Y. N738970 SIG_INTEGRITY GEOMETRY_EXTRACT power bus issue with SSN simulation when device is on bottom8 J9 L# H5 p L( j. X& b
744762 CONCEPT_HDL OTHER Connection dot sizes do not match on printout vs. screen( z& f5 v" G/ D
750371 MODEL_INTEGRIT GUI Model name in physical view cann't match the model in right workspace, J4 T0 l0 L# F8 j" w; U
757024 CAPTURE STABILITY Capture crashes while exporting to EDIF
9 L! d0 H' C( z$ ^/ C2 v759094 CONSTRAINT_MGR INTERACTIV One member of a diff pair will show Analysis Failed when analyzing the design.
5 J4 P& |4 g9 B0 y/ s. O760178 ALLEGRO_EDITOR EXTRACT Crash Allegro when executing extracta command for big size design(size of .brd
* x0 ~* k& u7 A* x761391 SIG_EXPLORER OTHER Incorrect rise time% }( L5 ?- b, j3 w* }1 O. y7 [* @
762402 ALLEGRO_EDITOR MANUFACT When photoplot(RS274X) of MM unit was loaded, shape was broken.8 E% D z! c8 z6 j
762783 SIG_EXPLORER INTERACTIV sigxp - coupled tline on stackup layer should show solved impedance
4 J: `0 M3 R9 u+ \- [* O763150 ALLEGRO_EDITOR OTHER Request - IPC356 output truncate the padstack size to fit into the columns 59-62 and 64-674 d/ x. n/ {% S/ F0 X- g2 c6 H4 }! j7 z
763556 SIP_LAYOUT ASSY_RULE_CHECK Assembly Rules Checker is displaying an array of confusing DRC's on a Soldermask shape.
% ]4 t' ~) `- J( A9 B' m2 O r764399 SPECCTRA ROUTE Manually routed trace in Allegro are ripped OFF after routing in SPECCTRA using Route > Route Editor.# ?3 \7 L* g, M p) V5 ]
764475 SIG_EXPLORER INTERACTIV topologies from earlier versions cannot be opened in 16.2 on a machine
w& L9 h9 Z! ]) L765287 ALLEGRO_EDITOR PAD_EDITOR attempting to open padstack fails with - database has a non-recoverable corruption., j5 V0 p% t+ l: f. _2 ~# ]
766041 ALLEGRO_EDITOR OTHER Auto B/B via generator incorrectly defines some BB vias
5 A W3 g: g8 `3 W$ t766153 ALLEGRO_EDITOR SKILL Allegro crashes when trying to extract padstack information# \7 |6 N* Y8 ~3 l
766611 ALLEGRO_EDITOR EDIT_ETCH slide creates DRCs in ARK area
! b( o' j3 c- Z767041 CONCEPT_HDL CORE The tap command failed because the specified tap body CTAP is invalid8 X. w5 l4 b. v+ u" Z3 M) I
767146 FLOWS PROJMGR Project manager open last open .cpm in 15.7 version not in 16.3
0 \1 n `) k+ J# O; h767526 FLOWS PROJMGR Project Manager customization does not work
+ v. H2 I3 x- _: s6 j8 I767671 APD DATABASE Crash creating cline with axlDBCreatePath() on this database.
# k4 o3 _' c7 b: _! j& k767951 ALLEGRO_EDITOR DATABASE color net param file omits nets with bus brackets in the name
( A# V9 X) r# F7 h4 v$ U6 i768168 CONCEPT_HDL CORE Fontsize on instances changes when doing backannotation4 A5 p; O$ y* p. m, U" B) }
768207 CAPTURE STABILITY Capture crash while editing properties7 k) w( d$ r, v) B3 |
768734 CAPTURE PROPERTY_EDITOR Properties of title block are not getting editted through spread sheet.
- S0 X1 K0 A7 S8 A5 k768832 APD DRC_CONSTRAINTS Following Performance Advisor instructions results in much longer DRC check time.2 T3 v2 H. I( a
768990 F2B PACKAGERXL RFSIP architect 16.3 85Y Schematic to SiP fails due to softinclude in cds.lib file this problem does not occur on 16.2
6 o2 {3 h0 [' V0 L- s9 K769097 SIG_INTEGRITY GEOMETRY_EXTRACT Sip Digital SI-Bus Simulation function will shut down auomatically when it is running
( \8 z( c" l+ p# w/ T# S7 @. \769235 SPIF OTHER need to be able to remove mbs_spif* properties added by mbs2brd
! L4 k4 w% k5 ^5 i% y769326 CONSTRAINT_MGR DATABASE Length by Layer crashing2 `. N9 H5 m" f, B6 q( Y# q& K9 e
769336 ALLEGRO_EDITOR TESTPREP testprep density - returns Unable to add the PROBE_DENSITY subclasses.
( U2 {6 n7 R% Q- k) z I769458 ALLEGRO_EDITOR OTHER SMD Jumper has a problem about the connection point when using the Add Jumper
2 ^4 S: S! b! n( e3 F8 Z& H9 _* J0 _769845 ALLEGRO_EDITOR EDIT_ETCH Diffpair routing out affected by line to line spacing rule.
. E7 h* h% h3 l# `/ c769934 SIP_LAYOUT WIREBOND Duplicate Finger Name./ E5 p1 K, ]2 W/ E6 {6 N3 x9 m
770006 ALLEGRO_EDITOR OTHER Ratsnest_schedule[Power_AND_Ground] can not show figure without move symbol.3 U( u% K- L- b- j# s' o9 I
770125 ALLEGRO_EDITOR DATABASE PCB SI GXL Via Labels grayed out on formand labels not visible on the canvas
5 E0 A. j1 Z1 y' }+ ?770212 ALLEGRO_EDITOR DRC_CONSTR Incorrect Etch Turn under SMD pad DRC error on this board
) V7 \% r7 j+ T- N% [& o770230 ALLEGRO_EDITOR ARTWORK Artwork fails to suppress unconnected pads on pins with the net_short property.6 ^6 R+ m G4 J' G0 J# i
770233 ALLEGRO_EDITOR MANUFACT Fillets are not behaving as intended.
( P8 Y0 q( R' @+ a6 t770442 SCM PACKAGER Error during Export Physical - The subdesign block instances ares not updated with reuse properties0 \: A4 _ X5 Y, Z7 }8 W
770556 CONSTRAINT_MGR ANALYSIS PCB Editor's Constraint Manager not updating custom constraint cell.
! v5 f! C/ ]4 ?% e7 k770861 ALLEGRO_EDITOR PADS_IN PADS translation fails with no error message
6 y9 p6 T6 x( ?) y: }7 Z770872 SIG_INTEGRITY OTHER Opening Orcad PCB Editor for this board takes Performance License as well
% V+ b& @" W0 `! s" m771117 ALLEGRO_EDITOR DRC_CONSTR Allegro PCB Editor crashes on Update DRC-16.3/hotfix006& e# d# V7 I5 U7 P( y' f* i7 _
771181 ALLEGRO_EDITOR PLACEMENT Component deleted completely from board file after we Mirror and rotate them while moving them.5 w9 y/ W! |6 N" I- ]0 ]8 \* {
771256 ALLEGRO_EDITOR DRC_CONSTR Update DRC consumes system memory and crashes allegro after approx 30 minutes
% x# x' l& j3 s9 ^771423 ALLEGRO_EDITOR SHAPE Shapes - Update to Smooth - Low on available memory please exit the program.0 }% R4 i* }, S$ I0 s, {' [
771456 ALLEGRO_EDITOR EDIT_ETCH Allegro 16.3 crashes when using arrow keys3 w! e& J/ v; U* e. a; H6 F% P
771719 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license.
& q9 U, N& o# Z8 g. m {# T771765 ALLEGRO_EDITOR PADS_IN PADS translation fails to translate symbol/ P6 ]8 K) @2 u: B+ o
771766 ALLEGRO_EDITOR DRC_CONSTR Moving certain components takes a long time on this board database.
8 `- J7 C, L& U7 d( [/ B* I771815 SIP_LAYOUT IO_PLANNER SiP OA co-design flow does not allow a save to the .sip file after modifications in IOP
% d$ L3 u' d' O3 p, e3 f773072 SIP_LAYOUT ASSY_RULE_CHECK wire to wire same profile
: e8 S) }3 n, a/ _8 x773126 CONSTRAINT_MGR UI_FORMS Constraint Manager "Value Filtering" for Topology Schedule is missing TEMPLATE and "UserDefined"
- A' V( B& G: J& @ z; t" s773179 ALLEGRO_EDITOR PAD_EDITOR pad_designer crashed when attemting to delete internal name layer.
5 ~* k$ j! X- ^/ p" A773229 ALLEGRO_EDITOR OTHER Netrev never end importing netlist generated from Capture CIS
0 B$ C& ~% G1 W773329 ALLEGRO_EDITOR MANUFACT Allegro closes when performing a Linear dimensioning and then selecting the undo icon.
& H2 A# H4 D6 A* N# [% C" t773483 ALLEGRO_EDITOR MODULES place module problem
0 C- ^$ f9 o4 z) s774036 ALLEGRO_EDITOR INTERACTIV Rats not shown after move->mirror command6 g( k* l/ L" ~! f1 X2 ]: p
774170 ALLEGRO_EDITOR DATABASE DBDOCTOR fixes Error but it reappears and Artwork fails
0 k8 W) e( D& o; a. l9 T+ x( I774602 SCM OTHER ASA crash while working with hierarchy
" j8 Q& u3 q1 V774643 CONCEPT_HDL CORE DEHDL crash on edit of attributes2 C7 m5 s/ p2 Y8 C# b
775201 ALLEGRO_EDITOR SKILL Color palette can only be changed one time using skill commands2 P+ m4 V& L: H
775815 SIP_LAYOUT WIREBOND Unused wire profile once purged using wire profile editor are still available in CM and Color dialog* @5 P% d, J7 n6 s7 K' e- ]9 Q
775826 SIP_LAYOUT WIREBOND Cannot change the Wire Profiles on the wirebonds in this design
& U. ?; ^% D% F/ v775842 SIP_LAYOUT WIZARDS Die text in wizard is changing DIE location when origin set in DIE text file is other than 0, 0
+ ?( I2 a* T2 t8 V2 E; V/ g: P+ |4 }DATE: 04-23-2010 HOTFIX VERSION: 007$ W) X2 u7 a' \+ O( q+ N$ h
===================================================================================================================================2 a6 R7 w8 Y' C0 m: S8 `
CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 w' G7 V% D0 L; K% ?7 i# m===================================================================================================================================
L. e, i. W/ H5 m1 ]721859 ALLEGRO_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why?6 r8 I9 x" Z1 a
740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp
; I8 j" R: x( y' }744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools! {) r. f$ `9 q P
747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0.! V/ P5 t4 I1 ^" u, D" ^
747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash.
: M. I1 h1 @" a% P, W% [751372 CAPTURE OTHER Copy / Paste Issue in capture 16.3
5 j0 ^1 A8 n2 _% ~1 R1 E757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit.
8 U/ c7 N& F/ y1 _759906 CIS PART_MANAGER Property copy from one to several parts doesn't work
& _: w* N' N% \( K; _760154 PSPICE NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result# H1 I4 h7 c& I0 }. D/ a
761177 CIS OTHER Error Message - Memory exhausted
5 Z1 @" }5 f; a1 z762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location.
4 a" o3 p0 E. J4 w3 N( _763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.
; p: w" X5 d& O763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created.+ c& R& N" E# s% v
763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager?
! D- ~5 V- S/ D' E7 e764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.3
3 x% l6 x1 G! {$ C" |764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle.
1 `( C! [. ~5 G) |9 O ~/ A# m764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad
0 y6 j$ Z6 J% v! Q" y, m0 f764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.3
^0 \9 I* y/ x( j* O765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro( n2 W: a% _* t. d5 d# J
765319 APD DRC_CONSTRAINTS Identical Constraints in Performance Advisor question
" g4 A- u% h& X" w9 c0 }765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape., g9 `6 ~% n2 B/ V2 Y
766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle
% V4 D& ^$ K# V8 `! Q' C! H766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design
/ a* ^4 S/ V; L4 O4 Z+ }: A766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.3, ^$ z, p; @) O2 ?. t7 Y5 W
766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit( O }" y5 a }, |$ }
767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version.
; k" P0 F) d+ A0 ]# G767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step.5 G( t3 J6 o1 i' f" H; ^
767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs.
( O9 G# h+ ?/ k: R& c767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly
5 J4 R% `3 t2 l; Q2 {$ G9 Q768822 ALLEGRO_EDITOR SKILL axlSetParam return value is divided by 10 to the power of the design accuracy.
7 X( c; U& n. e) g769150 CIS PART_MANAGER Update All part Status on a group changes 揇o Not Stuff?status to 揝tuffed?in V61.3_ISR_5.
, i/ T8 S2 ?6 L% u% _! XDATE: 04-09-2010 HOTFIX VERSION: 006+ E/ Q& c0 H9 h8 c. k# T5 [/ r! }5 r
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
0 N: @& h. C/ ?% G! `===================================================================================================================================( K- u4 u8 w! ?2 w
745241 CONSTRAINT_MGR TECHFILE Importing a tcf file automatically enables On-Line DRC.3 ~$ `% [ a6 Y( k; f
752587 ALLEGRO_EDITOR PLACEMENT Uppercase File name(XX.mdd) for Placement replicate update on Linux.
9 C7 d1 {3 F# C753626 CONCEPT_HDL CORE newgenasym error while saving the hierarchical block symbol) v# U8 L8 y% r- S" E3 [! i; A
753894 CAPTURE OTHER Case sensitive version control S/W
& D/ ~+ I* m' @( F# _754487 RF_PCB OTHER Various asymmetrical clearance problems uncovered - calculation issues?
$ S4 u- b( F- ]2 L! d' D758272 CONSTRAINT_MGR UI_FORMS Entering values on the Min/Max Propagation Delays worksheet hangs the application.
' \; k( `& k# r5 H758911 PSPICE PROBE Pspice crashes while exporting probe data using our sample project* c7 z# ?0 p8 x# G$ c. M( u
759871 CAPTURE PROPERTY_EDITOR Save option in Right Mouse Click on property editor of nets doesn't saves all the changes.3 L4 T# M$ ~. o, e: d2 y4 S" y1 K
759890 SPECCTRA ROUTE Specctra autorouter ignoring prerouted nets. M* N6 ?. S; z9 {
760067 ALLEGRO_EDITOR SHAPE Dynamic Shape not getting filled on board with odd angle placement and routing
- D( M* c/ h) [/ \4 x0 B6 \760284 CONCEPT_HDL CORE Update Sheet Variables turns of the grid
' K& v; ~. K3 F* [- V, l1 ]/ [760480 MODEL_INTEGRIT OTHER Message open clipboard failed when trying to open the rename/reorder dialog in Model Integrity
6 y8 y+ b9 P; `) F# N760667 ALLEGRO_EDITOR PADS_IN The pads_in.exe translate incorrect drill shape from PADS 2005 ascii database." B: ?+ g$ p) U' s& m% F- @
760741 ALLEGRO_EDITOR MENTOR mbs2brd does not work in 16.3 but works in 16.2
" r8 o9 f2 W! i% B0 y. M8 F3 Y760810 CONSTRAINT_MGR INTERACTIV Deleting Region Deletes NCCs, M1 ^. p, w: r5 L5 ]. a
761114 PSPICE PROBE Refresh issue in Display > Cursor window
! }6 o4 Y% u; q- f& w7 S* c: D) p761180 ALLEGRO_EDITOR DRC_CONSTR Via_at_smd not working for custom shaped padstacks.$ p& x1 ?, [9 Z3 v
761305 SPIF OTHER Allegro crash when seleting any of the Route - PCB Router - submenu items.: {+ l, ^0 c- b) d
761376 ALLEGRO_EDITOR PAD_EDITOR Wizard_Template_Path is not considered for symbol template look-up ?
% W2 k8 {7 h( v+ T761416 ALLEGRO_EDITOR DATABASE Allegro crash on chaning the subclass for group of clines' ^0 [! M5 l3 A6 }( {% K& B) J- _# }" _6 y
761492 ALLEGRO_EDITOR SKILL about axlTransformObject function4 z1 a, F2 N) B, j5 w
761518 F2B PACKAGERXL about mismatch library path between cds.lib and actual) D0 X8 ?3 I3 ~- ~1 g7 V3 ?
761737 ALLEGRO_EDITOR OTHER Running Dbdoctor after executing Skill is giving symbol fit error for the .dra file
3 z2 A: u& N. ]4 K/ m762155 ALLEGRO_EDITOR SYMBOL Updating a symbol changes the netname of the cline resulting in drcs.( [. j* m' D$ v; ^$ ]1 S( K9 U, a
762181 ALLEGRO_EDITOR OTHER Allegro netrev crashes for long device name in PST* files9 ^7 n6 o7 M/ K1 i5 ~( U
762316 ALLEGRO_EDITOR MANUFACT Allegro disappears on Adding dimensions for the symbol file1 s5 M4 Y% W4 J& I& V/ e: U. \
762792 ALLEGRO_EDITOR PADS_IN PADS_IN fails for SPB 16.3
- k3 g x& d% f/ s763108 ALLEGRO_EDITOR SHAPE Z-copy shape create an error like VOID boundary may not cross itself
( T4 ~2 G. K! ~! M/ i( G763134 SIG_INTEGRITY SIMULATION Bit 7 of a simulation is out of sync with rest of bus. It should be the same for all bus values.
5 {, j. v9 K( I; c( e% L763149 CIS GEN_BOM CIS BOM in V16.3 is not correct if database has Quantity field and its value is 0.8 M" ~4 q: b& T3 ~! `) a7 I+ S
763296 ALLEGRO_EDITOR REFRESH The error was happened while doing the SUM
2 Y8 Y# U# N) o8 O763303 ALLEGRO_EDITOR OTHER SMD Jumper has a problem while using the Add Jumper B& s6 t( l w& O2 E1 d
763315 ALLEGRO_EDITOR PADS_IN pads_in got error message WARNING ERROR(SPMHDB-205)
0 s4 k: F& v! c6 @9 U& D+ e! L- H: m763354 ALLEGRO_EDITOR PADS_IN Auto suppress redundant shape while using pads_in translator& F% E ?/ L: a4 [1 t* ?# l6 l1 C; K
763428 ALLEGRO_EDITOR PADS_IN enhance pads_in.exe translate spacing and physical rule into Allegro.
- Q D: g+ ?& l* \& b763446 ALLEGRO_EDITOR REPORTS missing fillet is reporting pad without drill. ]+ }( o& C0 N
763448 ALLEGRO_EDITOR DRC_CONSTR Performance advisor shows Cset as unused nets when it is assigned to Diff pairs or xnets.
5 E, \/ {3 H3 }% l763586 ALLEGRO_EDITOR DATABASE Allegro rounds off the value after decimal in CM
% Y3 W( z* h- o! r2 |3 G |- u764077 CONCEPT_HDL CHECKPLUS The output predicate in the Graphical environment is not always returning the pin object for an output pin.
- ?# g6 h6 j! ~5 {# r$ C9 C& r! ]* GDATE: 03-26-2010 HOTFIX VERSION: 005! X) Q" d; h8 z5 l
===================================================================================================================================
3 g6 h6 m: |% d5 [9 `, ACCRID PRODUCT PRODUCTLEVEL2 TITLE
5 e& ]! ~$ Y- f, D2 d4 R$ x6 H===================================================================================================================================- S" s& a& e- A% c& g' B1 j$ W- H
599819 SIP_LAYOUT 3D_VIEWER display soldermask by default in the 3d viewer# G8 [4 U2 c" M) I4 P6 }4 a+ c
735992 CONCEPT_HDL CORE Create Test Schematic does not use the correct package type
" d, z' M0 C! Y. b5 P- G743787 SIG_EXPLORER OTHER 16.3 SigXP crash if sigxp.run created by previous version exist.! j$ p. D; n" R" Z" x" c
746320 CAPTURE NETLIST_ALLEGRO Remove Semi-colon from invalid pin-name check during netlisting! t. x3 A2 x- v0 n2 {
746444 ALLEGRO_EDITOR OTHER show element fails to display info on a via if it is in a module.
8 Y# S% }! N' D1 y5 ?746726 SIG_INTEGRITY SIGWAVE Save As and Open Dialogs open in last saved directory& s: X9 {8 x) Z" m$ O; z
750080 CAPTURE NETLIST_ALLEGRO Improve error message ERROR(SPCODD-390): |; M% x. a1 V4 i8 t- M, l; Z
750606 SIP_LAYOUT ASSY_RULE_CHECK Wire to BF same profile check
- [/ E% w8 ^7 ?3 G# r751492 CAPTURE FPGA Option to swap the pin-numbers rather than their locations in the Schematic after back-annotation
+ n5 d; |4 h* Z: G( m753834 CIS LINK_DATABASE_PA unable to link multiple database part/ ?6 U: t& k0 `* b3 U
753990 F2B PACKAGERXL Delay in opening the subdesign tab in the Export Physical setup in SPB 16.34 Q) Z2 X& R3 `( |$ o. S! q( o
754328 LAYOUT TRANSLATORS L2A gives error Subclass name TOP not valid Allegro subcls with s029 hotfix
$ _: }2 [# V _% k/ o4 H* a7 f* L8 y754434 CONSTRAINT_MGR OTHER allegro crashes when deleting matched group/ P) r9 x8 |; ]
755111 ALLEGRO_EDITOR INTERACTIV "ALT_SYMBOLS_HARD TRUE" property does not work when I mirrored symbol using move command in 16.3.# L4 h0 \6 J; S+ R ^
756131 PSPICE SIMULATOR Capture crashes while re-running simulation4 f8 q' U$ e4 @# ^$ M3 e. g
756148 PSPICE PROBE Zoom Area in Probe Window does not work for digital signal in SPB163
3 m/ x% y6 S9 t756169 SIG_EXPLORER OTHER Signal Explorer crashing due to sigsimcntl.dat
' \" W; w3 L# h/ p756176 PSPICE PROBE Trace color is wrongly interpreted in PSpice probe window.
) X ]- \7 x/ v5 l* H9 P6 B- A756224 SIG_INTEGRITY SIMULATION Simulation aborts reporting that VIA models have changed
$ M6 }1 r) {* }- U+ j7 d6 g" q w756281 ALLEGRO_EDITOR OTHER Why *.sav file cannot be recovered from PCB Editor utilities?4 b2 `) }/ b, C& _& D$ n
756673 SIP_LAYOUT ASSY_RULE_CHECK Running ADRC Metal to metal checks causes false X-D DRCs, cannot clear them and trying crashes the tool: n6 i' I0 ~ Z6 N l" R7 x
756918 ALLEGRO_EDITOR OTHER Allegro angular dimensions working incorrect in 16.3
0 a6 y; c% Z: @9 d' A5 k* ?) o8 y. }756932 ALLEGRO_EDITOR CREATE_SYM Create symbol fails with error duplicate pin number
' j% E$ B6 {2 y$ a9 X( b756976 ALLEGRO_EDITOR SKILL axlChangeWidth always return nil in Allegro version 16.3
2 S# [; V& G1 C4 M! I6 _9 s8 l757000 PSPICE NETLISTER Incorrect Hierarchical Format Netlist created
5 _5 n; c2 q1 y% \( f$ i757406 APD OTHER Implement Segment over void features in APD L3 x: p! n# M% R9 Y
757624 SIG_EXPLORER OTHER Sigxp runtime error when simulation is run and exit without saving the topology
+ u1 S6 R; w) o757820 ALLEGRO_EDITOR SHAPE Shape does not void to hole if there is no pad
# o$ o' q A# l( @758009 ALLEGRO_EDITOR OTHER Export > Library (MECH_SYM) adds a new subclass NCROUTE_PATH, data moved from one subclass to another.
3 X7 x: O. x W# H/ s758022 CAPTURE DRC Capture crash while running DRC with 揜un Physical Rules?checkbox.0 `5 s6 S% @" U5 H
758190 ALLEGRO_EDITOR PAD_EDITOR PCB Editor crashing on pin move in this design# ~/ n' t( p8 |
758374 F2B DESIGNVARI Problem with Mechanical part in Variant Editor
8 v3 C- @1 G& U' V# |) [5 @758471 SIG_INTEGRITY OTHER Differential impedance does not change on changing the etch effect values.
4 c: j a3 z' v0 A& v758490 CIS CRYSTAL_REPORTS Different crystal report output in 16.3 than from 16.2+ {5 q9 F0 S* h
758498 CAPTURE NETLISTS PCB Editor netlister hangs
5 e+ t0 `* l% v. X' M' H758584 APD SHAPE Shape not voiding all elements
, h5 Z0 K0 r+ P, K0 H# K0 L9 A758886 ALLEGRO_EDITOR REPORTS Total number of nets is wrong into Testprep Report
) n3 q- z; h9 b1 k$ P9 F' M759146 ALLEGRO_EDITOR SKILL The title is not displayed in the form by the version.0 i1 y; y7 y5 d+ k1 y. a
759339 ALLEGRO_EDITOR ARTWORK artwork output fails by SPB16.x.) B/ k% ^; n1 I
759591 ALLEGRO_EDITOR SKILL axlSetParam fails and does not round the value as indicated by the warning message+ H' B7 S# ?4 x6 a
759816 CONSTRAINT_MGR OTHER Allegro Hangs when double click on a Bus in CM
- K1 c. b( Z- J5 y759947 APD OTHER Need an a way to convert Lines into Clines9 j. y$ d6 X( O3 }3 C1 u
760353 ALLEGRO_EDITOR MANUFACT Allegro crashes and creates a .sav file on running the silkscreen command from Manufacture > Silkscreen
; k+ }) x) N- i# P3 U760432 ALLEGRO_EDITOR PARTITION Unable to remove fixed property after partition import3 q6 ^5 g; n. Q2 J# Y+ B
760638 ALLEGRO_EDITOR PADS_IN pads_in translator can not handle " PINPAIRGROUP ".
2 z' o; s( y) C: w" O4 i4 l3 Z760734 ALLEGRO_EDITOR SHAPE Different therma contacts on rotated partsl
- }! o9 H7 o% \+ s761436 CAPTURE NETLIST_ALLEGRO SPCODD-53 Error when creating netlist with PACK_SHORT
! S9 D$ j" X) S! M% C( e |DATE: 03-12-2010 HOTFIX VERSION: 004) Y+ n$ m. c4 R* a: J& n
===================================================================================================================================
l6 T; V# h) v. R: iCCRID PRODUCT PRODUCTLEVEL2 TITLE
8 m. B# X- Y: H3 c0 A7 @+ H===================================================================================================================================
! }% C" K( |1 P; `) Z689495 ALLEGRO_EDITOR DATABASE corrupt database) ^; R0 d7 @, g a7 ]% L8 i
725944 SIG_INTEGRITY GEOMETRY_EXTRACT xtalk make allegro freeze and never give hands+ | z9 K* t4 h+ c& ?4 ]: C) F
732604 SIP_LAYOUT SHAPE Shape Issue - added shape will not clear around other elements./ i/ N6 O& E/ P( \: Z' H n
740106 PSPICE NETLISTER The "Enable PSpice AA Support for Legacy" option does not give the Desired Monte Carlo results
* k/ P& @% B2 y8 u744259 SCM UI Signal order reversed when a Vectored Signal name is renamed in reverse
/ I0 [/ R- z) o; l8 S1 x% m" F% Q8 `745554 SIG_INTEGRITY GEOMETRY_EXTRACT Time to get Xtalk simulation result in 16.2 is lower than acceptable by comparing the time in 15.7, q6 z# m" n# }2 n5 c/ L
745595 RF_PCB FE_IFF_IMPORT import iff RF_PCB give an empty block
! Y5 |9 r- m" r4 W747133 CAPTURE STABILITY ERROR [DSM0006] Unable to save7 y) N5 Y" R, H9 X7 v5 G/ v
747679 CAPTURE STABILITY Trying to Save the Design in 16.2 format gives DSM0006 Error and crashes Capture
& X' M& \- W/ F. W750460 CIS FOOTPRINT_VIEW 3D footprint viewer doesn't shows the footprints
1 }2 D7 K5 m" v0 r750777 SIG_INTEGRITY OTHER Trace impedance showing wrong2 Y+ c9 U n; w6 @0 j7 c
751424 ALLEGRO_EDITOR DRC_CONSTR Unexpacted DRC for Shape to Route Keepout
6 @* B7 r7 i3 u! n751897 SIP_LAYOUT SPECCTRA_IF Radial Router crashing SiP tool
, E) U$ S/ L8 L- Z752029 SCM OTHER Cross probing not working between SCM and Allegro Editor in Linux Environment' M3 p8 A+ ]: U
752450 APD PADSTACK_EDITOR APD crashes when selecting a User Definable Mask Layers.
; ~2 h) B, \" l( z$ \; }0 _$ V752581 PSPICE PROBE Pspice probe window crash/ ~/ h2 ?5 v: ^3 l
752709 ALLEGRO_EDITOR PLOTTING Sheet content doesnot plots title block! T8 x3 G0 j a) R
752908 ALLEGRO_EDITOR INTERFACES Output from Export > DXF shows one instance of a via on the wrong layer0 K$ D2 g" i7 U
753226 ALLEGRO_EDITOR OTHER File > Change Editor doesn't shows the default Product Options& \+ h3 F& N! a" D; x/ W7 v/ Z6 i7 S
753622 ALLEGRO_EDITOR GRAPHICS Enahnce capture image command to default the save as location to working dir8 \, H" B8 \% B! _. s5 I6 u' J' m6 M
753773 APD WIREBOND Requesting the option to set the diameter of the default WB_TACKPOINT power ring pad.8 h" V) u: p- W0 x/ i2 G% V
753778 APD IMPORT_DATA Import NA2 displays the design momentarily and then crashes
$ J/ d& V( B- C- r# b753866 SIG_INTEGRITY OTHER about Select by Polygon after move command1 Z! E9 H7 Z$ o
753958 CAPTURE OTHER Capture V16.3 is extremely slow while edting schematics of design placed on network drive via VPN. d' j* t- @, {8 } K
754050 ALLEGRO_EDITOR UI_FORMS Why show element window disappears when scriptmode is set invisible
1 t& @9 O0 H1 B754143 SIP_LAYOUT OTHER SiP Package Design Integrity - running Extra Cline segments generates report without Layer number, K- j7 \" ]$ e- V4 C( }- T
754327 ALLEGRO_EDITOR OTHER Rename Sub Class is not working as desired.
! H- [# s4 S" [# l" n! i754364 ALLEGRO_EDITOR PLACEMENT Crash when applying placement replication
* n* p, p3 P, l, J754462 ALLEGRO_EDITOR SHAPE Allegro circular dynamic shape fails to fill2 \( M6 t8 m; b# X" v
754819 ALLEGRO_EDITOR OTHER Create details shows wrong graphics for filled curves
) Q8 e( e) S$ W755176 ALLEGRO_EDITOR PADS_IN Pads translation succeeds in v16.2 but fails in v16.3 on this ASCII file% m( F% {# e% t [9 @5 P
755256 ALLEGRO_EDITOR OTHER Attached script is crashing the designs in v16.34 K7 `7 w- D8 r' v2 H9 k
755610 CONCEPT_HDL CREFER Cref hyper links does not work for signals where number "0" used to define the zone for page border* p- N8 m, }) X k
755787 ALLEGRO_EDITOR EDIT_ETCH crash using resize_respace_dp command& I& q: u& c2 I* [: K. R% ]
755881 ALLEGRO_EDITOR DATABASE Swap component crashes application7 ]( T! y) D! Q9 B0 K0 ~& m
756092 CAPTURE PROPERTY_EDITOR property editor flickers and loops on value edits! E3 Y* r# V( N
DATE: 02-23-2010 HOTFIX VERSION: 003# l/ X d$ n: B
===================================================================================================================================: Z; O! X) J1 g5 b/ u
CCRID PRODUCT PRODUCTLEVEL2 TITLE
! }: ]: F7 q1 v3 y3 U8 ~ o===================================================================================================================================
; ~- U# G6 u. T3 T) F1 M263504 CONCEPT_HDL CHECKPLUS Checkplus fails to run if crefrpt exists in the design% o% G+ y! T: N" w8 Y& m- I6 h7 M
726836 ALLEGRO_EDITOR SKILL axlGeo2Str() and axlGeoEqual() return different results
9 U7 H# l/ v& E1 ~9 v' g6 W730820 SIP_LAYOUT PADSTACK_EDITOR Changing the Via diameter will cause the SiP tool to crash
4 m" P3 b: V6 m: Y+ H735193 CAPTURE FONTS Pin_names and Pin_numbers get convertred into darkened blocks in 慫oom to all?view in V16.2.* {$ B! O4 [+ b/ ~5 }
737307 SIG_INTEGRITY GEOMETRY_EXTRACT differential pair extraction to sigxp fails to extract coupled sparam via models
+ B K0 V* w' {! z740936 ALLEGRO_EDITOR SYMBOL Confusing error message during Create Symbol* d1 E, }$ ~1 m% E t; |& l9 l# n
744191 ALLEGRO_EDITOR EDIT_ETCH Arc routing enhancement
$ P! p0 {4 i* G( F8 \744497 ALLEGRO_EDITOR INTERACTIV PCB Editor Crashes with Data Customization Feature
1 W. D6 F0 O! a4 O6 h: N+ V746572 ALLEGRO_EDITOR DATABASE Reoccuring error in attribute pointer to attribute invalid on dra.
+ L, {$ Q0 K3 U% [) h6 H' u746978 SIG_INTEGRITY SIGWAVE 2 licenses were used for SigXP and SigWave. U0 o) m$ b1 x' g
747219 SIP_LAYOUT SHAPE Dynamic Filleting not working with odd angles
( P2 U# X4 J. R- X9 i5 ?747593 ALLEGRO_EDITOR PADS_IN Some RULE_SETS cause the PADS translation to fail./ }9 P5 w e' U i3 p
747746 ALLEGRO_EDITOR OTHER Request for more detail in downrev.log file# z4 I5 C: d" |
748033 GRE IFP_INTERACTIVE Enhancement in GRE where Show Element on Bundleshould show the total number of nets that are part of the bundle
6 ], {+ l$ |4 k) u748333 ALLEGRO_EDITOR OTHER place by schematic page number not showing pages correctly; d: ~* [" ]) B8 }
748375 ALLEGRO_EDITOR MANUFACT gloss - line smoothing causes crash; w, V7 J, s5 G0 Q
748818 ALLEGRO_EDITOR DRC_CONSTR Undesired DRCs shown in allegro 16.3 while moving component and the same are removed by update DRC
$ o+ Q( x2 Y4 y2 w748865 CONSTRAINT_MGR OTHER Allegro 16.3 slow to move component with CM open
+ Q$ l3 k/ d( T: Q7 @6 ^6 B; A. D749009 APD WIREBOND a part of function of the finger alinement doesn't work" B2 [% ]0 _& C" f$ i+ |
749162 SIG_EXPLORER INTERACTIV Unable to proceed after RMB > Preference > Cancel
" x9 _3 a5 P! E749307 ALLEGRO_EDITOR MENTOR mbs2brd fails with error VIF_Allegro_Write
7 ]+ ` ]& ^. _# E" f: o, r749435 CIS DESIGN_VARIANT Cannot create variant part in 16.3
, [: L! g1 X0 m- c, `749854 APD PADSTACK_EDITOR The value of user-defined mask layer is not retained in the design.
% T- @% p' u( D% `* J9 T749891 ALLEGRO_EDITOR PARTITION Unable to delete existing partitions
5 c& @ K) n |749949 SIG_EXPLORER EXTRACTTOP A Topology extraction fails using APD and SiP series with the latest hotfix(SPB16.30.001).0 }" i5 }6 d& z
750008 CAPTURE NETLIST_ALLEGRO Netlist different in SPB 16.3 and after installing SPB 16.3 hotfix 1
# c/ c0 N# U! ^750591 ALLEGRO_EDITOR DATABASE Analyze diff pair object fails to display uncopled lenght values.
r0 q2 ^8 J; s8 ~% {# r. L750888 SPECCTRA ROUTE specctra is crashing while routing7 L9 N7 Y4 M" U5 w$ E5 s
751204 F2B DESIGNVARI Design difference crashes while reading funcview
' O. Q8 U. O# C3 \751398 ALLEGRO_EDITOR OTHER Allegro Crash when Edit is selected in Setup > Outline > Room outline& @ M4 j+ n/ t. N: f
751578 ALLEGRO_EDITOR PADS_IN pads_in hangs while conversion
) G8 ?2 P1 A! w; Q2 w W2 `DATE: 02-09-2010 HOTFIX VERSION: 002
& l; E; D+ K0 c1 R6 c===================================================================================================================================
u9 x: A% j P3 N0 \CCRID PRODUCT PRODUCTLEVEL2 TITLE
% I& S/ F7 m. m( D6 V. Z===================================================================================================================================* t" L$ ?( W, S% k% W& n$ f0 Z e
527012 SIG_INTEGRITY IRDROP Severe Memory leak in IRDrop( F$ ?. K L! N r% n1 W
623678 PCB_LIBRARIAN CORE PDV freezes when changing grid
9 J' D1 L! e8 A! T) Q8 A672592 ALLEGRO_EDITOR SHAPE Shape does not void correctly untill a clearance oversize value is added
# Y h2 E2 b6 w6 ]2 o- k7 j688062 PCB_LIBRARIAN CORE PDV Strange characters appear when copying text into Bus Arrows ( Text symbols)
4 W3 w0 }, x& x* B710170 SIG_INTEGRITY IRDROP Run IR Drop even if all components on the net are not placed.7 V! w7 y; S- v. J! v
710174 SIG_INTEGRITY IRDROP Audit function for IR Drop.5 v# F2 Z9 v: N/ i- e$ V. }1 E+ K k
726833 PSPICE DEHDL Modify the methodology for migrating 15.7 and 16.2 users of ConceptPSpice
: L+ E$ u) S7 O1 w. B730717 SCM UI Unable to delete a zero connection signal in SLP which has a pull-up
0 A4 a$ V5 u# h1 b6 X0 z3 b/ B3 j- j731017 ALLEGRO_EDITOR DRC_CONSTR DRC's show out of date when artwork is run
( p/ \0 g$ J6 R& P/ s8 w732145 CONCEPT_HDL OTHER Incorrectly generated VHDL netlist* A, y9 h5 c+ o
740123 ALLEGRO_EDITOR GRAPHICS Capture Image command fillin missing from jrl and script files1 Z: E4 P* s6 `0 P: Z9 s
740278 ALLEGRO_EDITOR OTHER Jumper fucntion for Single Side PCB Design
5 P' k& ^# h: } c; C9 t740656 ALLEGRO_EDITOR GRAPHICS Can we place custdatatips.cdt file on a site level for SPB16.38 m( U7 j1 q4 K6 q% ?4 [. `
741222 CONCEPT_HDL CORE Replace command (in Windows mode) causes crash# v) d' X1 U' M8 }, \0 |
742389 ALLEGRO_EDITOR EDIT_ETCH Change or add message when using Countour route
7 b$ \. s. @; p3 g: U, M, [. S743275 APD DATABASE With DRC enabled, this design seg faults in axldbid.c (solaris only). DRC update takes orders of magnitude longer on sun
# U; A* a6 ?* s0 S! O& F9 O/ ~743623 F2B PACKAGERXL Pxl error when using pack_ignore on reuse blocks
0 ?' t: W8 N4 l2 t9 }% o744348 F2B BOM PART_NAME column getting word wrapped inspite of sufficient space in the HTML BOM report.* n* @1 t, G$ E. k! z+ ]
745062 CONSTRAINT_MGR OTHER import techfile does not add new layers in cross section' o* R& F& O3 {
745148 ALLEGRO_EDITOR GRAPHICS Allegro ptf driven HEIGHT value not pushed into 3D Viewer
, p6 b2 Z: {' J/ |- d8 O6 k. m745301 ALLEGRO_EDITOR DATABASE Allegro 16.3 crsh on moving component
/ v7 }7 P5 `1 v: L6 a745518 ALLEGRO_EDITOR DRC_CONSTR DRCs not shown when "Enable Antipads as Route keepout is checked in"
0 P" Y9 ~+ D! R% v( q/ N) @% i6 {745745 SIP_LAYOUT WIZARDS Die Text In changing the pin names on duplicates/ R. T/ Z- X% e; y- B% r
745785 CONSTRAINT_MGR UI_FORMS Unnecessary window opens when the cell in PCSet By layer worksheet was clicked.
7 c" c0 p8 T, M. d, f746002 CONCEPT_HDL CREFER Could not find pc.db in the root design
0 @: ^+ {7 m }3 M/ r3 o$ _4 c746010 CONSTRAINT_MGR SCHEM_FTB Updating the brd file using the "Import Changes Only" option overwrites the modified constraints in
9 |1 I' P) X7 |+ D' b4 {. S746080 CONSTRAINT_MGR OTHER Click Constraint Manager filter icons crash software, e% K+ d# _. u- k
746137 APD IMPORT_DATA Import > NA2 not transalating certain layers and padstack sizes# G9 P( l+ G8 f7 O$ G9 Q
746370 ALLEGRO_EDITOR GRAPHICS Setting infinite_cursor_bug_nt variable flips mouse movement on flip design
0 g% H/ z* A, i: { b5 g746519 CONCEPT_HDL CHECKPLUS CheckPlus the if statement is not seeing the True condition or the output predicate is not returning the True condition.
# V" Q3 Y; f) F4 B746546 PCB_LIBRARIAN VERIFICATION con2con choosing incorrect PART_NAME in PTF File during verification
9 E$ }( W: q/ ]& W& y746865 CONCEPT_HDL CORE Tool generated pspice net names in core concept design cause short with copy all.
3 Z3 b5 q, O$ ?747636 SIP_RF OTHER RFSIP Layout RF Module Export chips & connectivity is not writing die attach method to chips file
' ]7 R8 T& q2 A9 N6 l* I" j) E7 qDATE: 01-31-2010 HOTFIX VERSION: 001
" g4 ] ?* c) {6 l===================================================================================================================================3 {* s2 b; e7 A- O
CCRID PRODUCT PRODUCTLEVEL2 TITLE
% h8 P3 ?7 q u, E' a===================================================================================================================================* ~9 M, ^ l: }9 w7 i
491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute
1 y' O$ z0 g; T0 n, T496910 CAPTURE NETLIST_ALLEGRO Inconsistent netlist creation# J4 y0 y6 [% P1 @
558783 PSPICE NETLISTER Why do Models with "awb*" prefix need wirte permissions to "*.ind" files?
1 C/ C/ t8 E& U, b" m/ R643241 CAPTURE SCHEMATIC_EDITOR OrCAD crashed while replacing cache1 p8 q" `1 K/ D: Z
654292 ALLEGRO_EDITOR DATABASE Propagation Delay constraint behaves differently between 16.01 and 16.2
8 M' Q, E5 ?) {+ K; d! R" a662829 CONCEPT_HDL GLOBALCHANGE Global Update should honor property visibility settings in ppt_optionset, Y, j: X# M* ~" |6 G
672718 SIP_LAYOUT EXPORT_DATA "Export>Symbol Spreadsheet" should export a .cvf not a .txt
' ]& L8 B- I* R1 t0 q1 l- k/ q676233 CAPTURE NETLIST_ALLEGRO Cross probing stops working if design name has dots1 \: F- [, V$ ~3 j+ W' D9 I( `
678739 CONCEPT_HDL CONSTRAINT_MGR Manually added targets in matchgroups lost when reopen CM
) v. ?! P2 w5 A* C690618 F2B BOM Write protected template.bom fails to write callouts( p4 B) \* d8 f# r* V
700246 CIS LINK_DATABASE_PA Need option to update symbol always when linking part in CIS8 u1 K0 U. y! |, k* ~- |4 S
705393 CONCEPT_HDL CORE ConceptHDL crashes while switching to another hierarchy level under File > Plot Preview.+ s6 Z6 X$ A: e8 m8 `
708634 ALLEGRO_EDITOR SHAPE Shapes getting incorrectly displayed in 16.23 [# h( ?; D/ `- L% C V
708950 CONCEPT_HDL CORE Tool crashes while trying to change the text on the schematic using a text editor.# k8 N4 ? W5 K/ ]
709823 ALLEGRO_EDITOR OTHER Arcs not converted properly when upgrading symbols
# T$ w+ i/ t' L D4 R( `4 m713964 F2B PACKAGERXL Net property Probe_Number is getting changed during the packaging run' d* M) }& o0 p+ v. `
718119 F2B BOM Exclude the callout file name from the template.bom file; O8 L% q- g2 b' D0 {& O% F3 f3 V, }
718496 SIG_INTEGRITY SIGWAVE Frequency at smith chart.
( s7 w" Y* i4 f7 w9 D9 U9 j: q( v) C721422 CONCEPT_HDL CHECKPLUS Checkplus fails if "\\" character is used in the parameter list
7 C+ b" ^/ F& _+ x, O721788 SCM OTHER SCM unresponsive while closing out a Block without Saving" `: W5 W( i6 ~4 i/ `9 A
721801 CONCEPT_HDL CORE Save As crashes DE HDL if an existing page is selected in the design
- ?8 |/ x) H! Q2 T; j" N9 t722653 F2B PACKAGERXL Packaging does not complete
" h. F: K4 k2 L: L1 j- j725285 CONCEPT_HDL CORE nconcepthdl does not work same as concepthdl for same script.* C2 @) { e& Q# J
725719 CONCEPT_HDL CORE wire pettern of Publish PDF
+ d% s: M+ x0 }. n* Q- G. H727062 CONCEPT_HDL CREFER Custom properties not visible for TOC symbol in schref_1 view7 G3 Y0 E5 o. }9 p
727194 CAPTURE CORRUPT_DESIGN Random Capture crash
5 p& |" y9 _! e' z727704 SCM PACKAGER ASA to PCB getting out of sync
4 c" M$ N! |# v3 v. b# T3 t728066 CAPTURE NETLIST_ALLEGRO Allegro PCB Edtior net cannot be generated if PACK_SHORT is used+ N* S% U7 `. }7 p2 s7 c; ~
729214 CONCEPT_HDL CORE SHOW_PNN_SIGNAME directive used with Windows Mode gives crash6 ^3 s3 R. R. W8 _" T
730295 SIG_INTEGRITY OTHER Filled rectangle shapes not extracted properly |* `4 y) ^4 i0 x
731183 CIS QUERY_DATABASE CIS Query fails with ODBC Error for query (Price contains 29)
9 N" x3 T; X0 B2 G" Z732073 SIP_LAYOUT DXF_IF DXF_OUT generate an incorrect shape
. C" X- q3 z6 g' r1 b _' f4 v732138 CONCEPT_HDL CORE Cannot change SI model assignments( |7 `% K5 [+ n8 l' C
732216 ADW DBEDITOR dbeditor crashes doing copy-as-new into lib folder that has partially completed chips.prt file
+ l) j4 N& u+ A5 k% v732249 SIG_INTEGRITY SIMULATION Probe sim with custom stimulus cause segmentation fault. Linux only.2 O0 x4 Y2 k3 d% d# D
732847 ALLEGRO_EDITOR DRC_CONSTR Manual Void uses Shape to Pin constraint to void Holes9 k- M% {& E5 b: G y
733261 FLOWS PROJMGR Project manager does not work with the Restricted User in client server environment
; Q6 ?. d1 `' t# g733773 CONCEPT_HDL OTHER Syntax issues in DEHDL
" N1 p0 N l) a+ ]9 A. v734260 APD COLOR Why subclasses still remain visible even after global visibility is turned off.4 x4 F( F* n; O+ H
734419 CONCEPT_HDL CORE Concept crashes in windows mode when netname is deleted on schematics generated by ASA
5 C! A! N% |7 y- g3 ?% e) Z4 G0 v$ _% y734555 CONSTRAINT_MGR SCHEM_FTB Import Logic does not overwrite the Constraints
# e5 \' ]# i4 E735290 CONCEPT_HDL OTHER Concept's PDF Publisher has issues.* J) @$ B( j+ V \
735892 CONCEPT_HDL CORE "Component Modify" changes visiblilty of Key properties
, s2 _3 f `' \# S735977 ALLEGRO_EDITOR MENTOR Mentor to Allegro translation fails without any error message0 C" u4 H4 l5 V9 t( Z/ }
736071 CONCEPT_HDL CORE Property visibility is not retained on the schematic instance when we modify the component on sch.
# ~2 U. c' s3 N2 s, P. i$ P7 O736165 SIP_LAYOUT SCHEMATIC_FTB about error message of "schematic to layout"
: u" f. O, A+ U/ p' x( M736167 CONCEPT_HDL CORE HDL crashes when I select BGA symbol in Component Browser
% [3 T* G+ f t$ R( v736911 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge
! e- H2 g0 B% W6 ]738035 ALLEGRO_EDITOR OTHER Measure function has different result between 15.7 and 16.2 version.; ?) N% p, @9 Y
738129 CONSTRAINT_MGR UI_FORMS Need Diffpair Constraints option in Analysis Modes Electrical Options with Performance license
* u, M* T; i. b( J738276 ALLEGRO_EDITOR PLACEMENT No feedback in console window when placing unfound components in Allgero 16.3& u% y5 _ a2 t5 j: b
738366 ALLEGRO_EDITOR GRAPHICS 3d viewer not showing some connectors with mutliple place bounds correctly2 T+ V9 a" z& A: K: y" V8 @1 a
738454 SIG_INTEGRITY FIELD_SOLVERS EMS2D extracts incorrect CPW to Trace spacing
3 o& B/ z: p' C' ~4 b/ }738578 ALLEGRO_EDITOR OTHER scriptmode +w doesnot work on Linux% J) e) h# \" m, A. X9 m' A
738869 ALLEGRO_EDITOR OTHER Error msg when cds.lib contains missing SOFTINCLUDE
& H3 j% J* U# @. ? h |739116 EMI SIMULATION At EMI simulation on SigXP an extra Sigwave form is launched.
, @" M/ n: ]4 R- K; K4 x: P739225 ALLEGRO_EDITOR GRAPHICS Ability to lock the 'Hide Pallette' option
; q/ A) ^; D6 q) n [# @739599 ALLEGRO_EDITOR DRC_CONSTR drc_errchk indic& Y7 B# P, x& @! q" N& P, J
739628 ALLEGRO_EDITOR SYMBOL Opening a symbol file is crashing allegro.5 H. Q" d( N @
739653 ALLEGRO_EDITOR SHAPE Shape created in 15.X .dra changes geometry when uprev'd to 16.X
7 B# f; h7 O) S/ F0 I, ]739661 ALLEGRO_EDITOR OTHER Export netlist creates incorrect via_list syntax. @9 q! e" ?! T7 X! X1 d
739872 ALLEGRO_EDITOR SKILL Crash while performing axlExtractToFile in 16.30 T( W. S+ x4 ?9 g2 [ f
739934 SIG_INTEGRITY OTHER specctraquest crash on changing signal model
' Z/ ]; W' i, r$ I/ K( ~739937 MODEL_INTEGRIT PARSE zero valued estimated parasitics in ibis models
' z7 |: Y8 i4 J- B8 l' c/ z! T739942 ALLEGRO_EDITOR SHAPE zcopy xhatch shape creates oversize copy
% C3 n \; Z. X/ Q+ z5 \740133 ALLEGRO_EDITOR DRC_CONSTR Same net DRC Update from Analysis Modes runs forever.* ]4 @$ R9 F% c) V; ~0 s( i
740281 ALLEGRO_EDITOR OTHER Jumper components where were placed in PCB disappeared4 W3 t7 a. E* T8 Q0 n
740309 SIP_LAYOUT DIE_EDITOR Moving a die pad in DIE EDITOR on G69A_U1 causes the die pads to rotate 90 degrees from the design.
$ e8 J2 Y) `$ Z. q: \$ o" \! i740399 ALLEGRO_EDITOR COLOR Cannot automatically load custom color palette in 16.25 Q" b, j* G$ z& N
741210 ALLEGRO_EDITOR DATABASE Edit >Move; spin creates 'connect record not found' message
4 |5 m6 `! i- {2 n: v741307 ALLEGRO_EDITOR PADS_IN Shapes on some layers is not getting translated from PADS into Allegro
8 Q4 I7 T6 F) T5 \- M" R741313 ALLEGRO_EDITOR DRC_CONSTR Add connect slow in 16.3/ V/ r$ s4 n: K2 J
741778 ALLEGRO_EDITOR COLOR Color pallete in 16.3 is not expanding when maximize dialog7 S% _5 m& R5 c
741910 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd
1 P4 L/ k( q5 j: {' Y3 m741939 ALLEGRO_EDITOR PADS_IN PADS to Allegro Translation fails or hangs.% n) C9 @! m0 X+ K1 a
741980 ALLEGRO_EDITOR PARTITION Import of parition does not import etch or vias.! c, v! |, L1 @
742676 ALLEGRO_EDITOR SKILL Tpoint cannot be moved by using skill.% l+ D1 G8 i; m9 C( @8 L9 H! g
743161 ALLEGRO_EDITOR SCHEM_FTB Netrev crashing when importing netlist into board file.
6 U; p3 L: p* _9 C& {( ~0 x743235 ALLEGRO_EDITOR PLACEMENT Allegro crashes when unmatching comp in placement replicate.+ ~! h, S: J9 G a' {* f
743243 CONSTRAINT_MGR TECHFILE Closing CM destroys tcf values when they are set to locked using fObjectNOTReadOnly8 V. ?! i3 u% B
743301 SIP_LAYOUT DIE_EDITOR Edit die command creates two extra die pads6 G5 V/ G; v8 I% z% H- x! o
743316 CONSTRAINT_MGR DATABASE With Allegro 16.3 Constraint manager takes to long to update, }# L0 ?. z- Y. g
743553 CONSTRAINT_MGR OTHER Net disappears if we cancel the line width edits in CM |
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发表于 2010-6-3 12:25
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