正版的才能见到的官方网站上的SKILL

yejingang · 发表于 2008-12-28 19:56

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http://www.3zonline.com.cn/bbs/index.asp?boardid=8
官网上才有的SKILL
还有关于SKILL的说明文档
这个包里面基本上都涵盖了所有的SKILL了（前提是你能用到几个）
Allegro SKILL Code
Important: The code in this library is provided "As is" and is not supported by Cadence.

Users wishing to submit their SKILL files to be published in this library may do so by submitting a SourceLink Solution
Important: The code in this library is provided "As is" and is not supported by Cadence.

Allegro SKILL Code
Important: The code in this library is provided "As is" and is not supported by Cadence.
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Get all files shown below (zipped archive: approx. 415 KB).
Add assembly reference designators
Add assembly rulers
Add filled rectangles on etch layer to provide balance during plating process
Add pinuse codes from schematic as Allegro properties
Add a property to all vias on a net at once.
Add a filled circle to the active layer.
Add text variables to the brd drawing automatically
Align symbols
Allows user to add a symbol to the design (For Allegro 14.0)
Allegro to Capture backannotation of pick and place data
Allegro to Fabmaster extraction utility.
APD - Graphical interface to create the IO connections file used by ZRouter
Assign DEVICE_LABEL property to components
Build a list of board files
Calculate QFP pitch
Change Cline Widths /Layer/Width
Check component changes between boards
Check the status of the dangling line report
Check if symbols exist
Convert between mils and mm
Convert text height in mils to match the database units
Copies the 14.x PACKAGE_HEIGHT_MIN/MAX properties to visible text for display and printing
Copy Shape to New Class or Subclass
Count SMD pads in a design
Create a report and add it to your report lists
Create a list of subclasses for given class
Create an Allegro plot
Create device files for use with third party netlist implementations
Create Thermal Flash
Cut Clines By a Graphical Window Selection
Cut a channel through clines by drawing a path through them.
Cut/Split power rings in APD Package Designs
Debugging aid which recursively dumps dbid info to a file in hierarchical format
Dehighlight all Dummy nets in a design  October 2007
Delete unconnected shapes in 8.1 - Source code
Delete all vias not on a net
Delete Signal Integrity FP_* properties from Allegro symbols
Display all DRC markers for a layer
Displays list of DRCs in a design and lets you "walk through" the list
Display assigned pinuse codes in Allegro  November 2008
Display utility for Datasheets using a URL
Display visibility control
Distance between 2 pts or from 0,0
Draw targets to line up paper/film plots
Etch visibility
Extract component height to a file.
Extract a netlist in IPC-D-356 format
Extract solder paste information
Fills class PACKAGE GEOMETRY/BODY_CENTER and draws circle with two diagonals in center of symbol
Find all dangling clines and dangling lines
Find and identify stubs
Find components from list
Find components over, under or equal to a user specified height value.
Find library path of each Allegro symbol and create a report
Find out of date dynamic shapes in 15.0 and later.
Flare connects into vias and pins
Function to determine whether a target point is within a circle
GUI to display scripts and replay them with a mouse click
Highlight Missing Pin Escapes Skill 8.1
Highlight Nets and Pins without Test Probes
Highlight only connected elements in a design  November 2008
Highlight padstacks from a list of component pin/via padstacks, and a list of drill sizes.
Initialize PADPATH variable for the manufacturing class you select
Interactive Net List Editor
List building utility.
List all rat T points in a design
Make a list of all the thermal flashes used in a padstack library
Make a list of all slots used in a padstack library
Merge Cshapes with pads
Mirror text
NCLEGEND List all NCLEGEND- subclasses in a design.
Place DRC markers on Device Pins that are missing a netname
Place by List
Place symbols and reference designators
Print number or point in design db accuracy
Redraws one or more objects in a different class with the same coordinates; transforms clines into shapes
Remove all externally generated DRCs from the design
Remove fillet properties on clines that are not actually fillets.
Remove hidden cline and via properties added to fanouts by SPECCTRA
Rename reference designators
Reorder artwork films in the artwork control form
Replace Via padstack by window
Replace PACKAGE_HEIGHT_MAX with value of HEIGHT property from ConceptHDL
Report 2d bonding wire to 3d length  October 2008
Report diff pair nets in a design.
Report first escape from pin, for Fully Buffered DIMM Design rule
Report short cline segments that are contained within the pad.
Report the product and version information of the currently running tool.
Report and highlight pins with the NO_DRC property
Report and Log File Viewer
Report and highlight single pin nets.
Resize the drawing extents to match database objects
Run DFA clearance checks referenced to the assembly subclass.
Save refdes locations from one file and read into another.  April 2008
Set the design origin using mouse selection.
Show component heights
Silkscreen violation checking utility
Techfile - Module to parse and import an XML Techfile August 2008
Unconnected shape report
Utility to unmirror vias in a design.
View DRC locations during shape cleanup after autovoid
Workaround for the SKILL axlLineXLine() function which fails for vertical and horizontal segments
Users wishing to submit their SKILL files to be published in this library may do so by submitting a SourceLink Solution
Important: The code in this library is provided "As is" and is not supported by Cadence.

[ 本帖最后由 yejingang 于 2008-12-28 19:58 编辑 ]