|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 紫菁 于 2017-9-14 16:05 编辑
* C& l# d* e0 M* `
* R8 x* x! @1 t c; f) L2 e8 ]' U$ C转 Hotfix_SPB17.20.015_wint_1of1
3 j9 N1 d. p0 d
: Z2 T1 `" d+ [/ C- J$ O' bFixed CCRs: SPB 17.2 HF015: Z. O# N2 c* G5 x9 V
03-16-2017
; E! g9 S* S* o+ y( M9 t========================================================================================================================================================
% L3 n z0 p$ x6 DCCRID Product ProductLevel2 Title
, r1 |( |* e( ~1 Y6 G4 F========================================================================================================================================================
6 s% c* y! |3 C0 a1653366 ALLEGRO_EDITOR INTERFACES Unable to attach step model to symbol3 Z. b' t, e+ Y7 o; I& X5 {* M) h
1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model
R: ^% G# F" i" }1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function. P7 X+ n/ x- }( b1 n7 [3 s7 Q3 F
1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file& Z" q% E! W6 E, a) f7 g4 H
1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting Padstack Editor results in incorrectly scaled forms
# H0 C9 r+ M' n/ f& W1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design$ ]. z9 O4 |# i. |" m/ g4 q" ^
1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees0 @6 H& J/ w; q
1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.& [2 S" U, M% S3 u; `
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously
0 m7 K' d0 G5 `+ K; g5 |" i* s1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor: S" V4 ?, |! ~: I
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not3 U4 {, H. ?3 t* {- {
1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used+ v4 t( B$ j7 x+ M
1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places* n4 X& I" d4 H# I) w
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value9 o3 [& E6 y8 L' W
1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically
3 L# v/ z2 ^# V' k1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad
* ]4 k8 Q5 C2 z& t* v5 w1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout# }8 S! M) M7 V# f$ A9 ]: i& Z
1698697 CONCEPT_HDL COPY_PROJECT Copy project corrupts the .dcf file: H+ r; f3 w0 f) |% \
1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 084
. Y) s5 L1 G" T* F5 y$ K" M1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position
) G/ e4 X! g2 J! a$ p# e1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net! ?( N% Y- [- x6 P- z/ G9 ^
1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer
( y, g) ]' m/ M o& N* d1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation
: {( P4 B( Q4 M" X1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates
4 q1 Z" C: u# Y# m1 f2 o5 W1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode. C/ O3 f. r! N1 o1 U) r
2 S, F# W) O3 J. N4 o转：Hotfix_SPB17.20.014_wint_1of1.exe 链接：http://pan.baidu.com/s/1jHFB2Pg 密码：mxnk' P) W1 Q# u- N1 a8 t) C
Fixed CCRs: SPB 17.2 HF014; b0 b R4 a/ Q& {& M
========================================================================================================================================================4 C% x( J2 @; V& k
CCRID Product ProductLevel2 Title
2 ]+ Z9 z( F+ j- w9 M5 \========================================================================================================================================================
/ P* W# z5 _+ |$ E* t" a1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships- k5 Y3 @' B' ~! i
1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity0 F+ r6 ]( c! m( V) M
1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-268+ T- h' @, a: `8 g2 p" M
1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data) u. G. L* H! l; N" Q2 B @ K2 ?
1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data
7 S/ N2 _6 y' m1 u, j9 Z* X1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors
4 b( F4 [% r5 T( Z1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.
$ T0 G! O, L- G; I- j$ z y8 b9 }1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted4 k" b5 J0 S0 s
1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location
5 B! r L$ o+ k1685995 ALLEGRO_EDITOR SKILL All film sequence numbers are returned as 0 when using the SKILL function axlGetParam
, T1 ]: j+ Z! C1 l7 C1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately ?: {) W1 I# W, ~% U5 W2 ^$ c
1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6
' ]$ f( x8 ~5 L1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one
, o% n: ~+ a- {# d' u9 ~1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled
4 k8 g+ _6 N, s) E1 L1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved
/ B4 `& V1 y* X2 T- a1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components
) |5 D4 F7 ^7 v1 Z- ~8 m+ d% H. ^1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers" ]- ~8 ^. X+ T7 n( h( z' G
1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase9 ~1 U& e' H) b) L4 N" Y
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement
/ w" T" J w6 ^) Q$ N5 M1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message
6 I8 ?! {, u9 b1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 011. w$ x/ [( H8 C& G5 }) ^% r
1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.27 S: ^! j! G. f
1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers
/ ?+ O! y" R9 C/ B6 h: a1 J, Y8 H1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016
( I4 m$ ]& a4 d" X8 p) j& t1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design& H" V8 t5 y8 D2 B8 Z
1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors5 [; h- B/ Z1 Z
1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters! }9 E( z( [1 C9 i
1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP9 ?2 q4 s0 c7 A8 d& e2 l) |
1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'1 _* u: E; D/ Q" u
1705265 INSTALLATION DOWNLOAD_MGR Problem installing OrCAD Library Builder from Download Manager
% O! Z1 S- O3 U1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script% n2 q, Z4 S$ M0 w! `: l: N) L5 X
. w! |3 R- ?4 n0 h/ XCadence OrCAD and Allegro 17.20.013 Hotfix链接：http://pan.baidu.com/s/1kVmHGZ9 密码：smsv
2 s. }' H+ ~; c% R2 c6 B% lFixed CCRs in SPB 17.2 HF013
+ t; J' \+ e9 }% d" h" z5 d4 }========================================================================================================================================================
4 P# `3 n) n0 Z4 i3 rCCRID Product ProductLevel2 Title
- x6 z5 z4 j! U2 M* ^ S9 ^========================================================================================================================================================: E' N: A9 k4 w
1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm' z% a0 w) ?4 L
1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer
, g H3 `4 s$ R! R X/ _6 n1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version0 k3 A9 I- a$ I. s2 ^" b5 {
1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated$ s( {2 O# L* G
1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated
9 V" r0 h8 O0 Z. i4 G' ^1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board
7 t v# q7 A. \& N+ Q( G) V1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor
) ~/ E" t1 I8 o& D/ b8 Y1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol4 J8 k; }* m/ p
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
* }6 P1 N+ }6 j6 v1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components
, O- D0 Y }' E/ F; r$ z1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components: p1 z8 c4 N- s# g1 w8 A. X% h3 O
1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets4 z& t3 c/ q8 E! l9 C: U. e# f
1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets
/ ]0 L7 B# \ p( ~3 `2 w1 p0 O% j3 o1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF
5 t r* S0 Y8 I! D$ `/ F: r0 k1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement
! E( C1 X7 t7 q4 C1 t% I4 o1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group., _- \: X' {, J9 h; I \% W
1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file5 w, X1 O: e1 X1 W U- H
1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.
. }* G8 ^ U3 y' j' W* A( u1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker6 M" ~0 D' N( m* K$ `* s2 I
1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates. G1 n& ^9 L2 e5 }: m3 K7 H, Q
1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes0 g) ^2 B% K( c3 ?0 F5 {& ?& D
1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side.! [; M- p5 U# @0 E- i* n
0 m" @1 @9 ?4 n
$ I" y. F5 H, R6 I6 ^% h; T; t5 Z2 u: }: b! ~
4 x0 [" L/ z! v( _ |
评分
-
查看全部评分
|
/1 
发表于 2017-2-26 17:05
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
楼主
发表于 2017-2-26 20:26
